Sense Amplifiers

ABSTRACT

The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.

CROSS-REFERENCE OF RELATED CASES

This application is related to the following U.S. Patents, which areassigned to the assignee of the present application, and are herebyincorporated by reference in their entirety:

-   -   U.S. Pat. No. 9,406,349, filed on May 2, 2014, entitled Memory        Elements and Cross Point Switches and Arrays for Same Using        Nonvolatile Nanotube Blocks;    -   U.S. Pat. No. 9,947,400, filed on Apr. 22, 2016, entitled        Methods for Enhanced State Retention Within a Resistive Change        Cell;    -   U.S. Pat. No. 9,917,139, filed on Dec. 20, 2016, entitled        Resistive Change Element Array Using Vertically Oriented Bit        Lines;    -   U.S. Pat. No. 10,096,601, filed on Jan. 30, 2018, entitled        Stacked Three-Dimensional Arrays of Two Terminal Nanotube        Switching Devices;    -   U.S. Pat. No. 10,204,682, filed on Sep. 18, 2017, entitled        Nonvolatile Nanotube Switches and Systems Using Same; and    -   U.S. Pat. No. 10,290,327, filed on Oct. 13, 2017, entitled        Devices and Methods for Accessing Resistive Change Elements in        Resistive Change Element Arrays.

This application is related to the following U.S. Patent ApplicationPublication, which is assigned to the assignee of the presentapplication, and is hereby incorporated by reference in its entirety:

-   -   U.S. Patent Application Publication No. 2019/0267081, filed on        Feb. 27, 2018, entitled Resistive Change Element Cells Sharing        Selection Devices.

BACKGROUND Technical Field

The present disclosure generally relates to resistive change elementarrays and devices for resistive change element arrays, and inparticular relates to programming and accessing resistive changeelements in resistive change element arrays.

Discussion of Related Art

Any discussion of the related art throughout this specification shouldin no way be considered as an admission that such art is widely known orforms part of the common general knowledge in the field.

Resistive change devices and arrays, often referred to as resistanceRAMs by those skilled in the art, are well known in the semiconductorindustry. Such devices and arrays, for example, include, but are notlimited to, phase change memory, solid electrolyte memory, metal oxideresistance memory, and carbon nanotube memory such as NRAM®.

Resistive change devices and arrays store information by adjusting aresistive change element, typically comprising some material that can beadjusted between a number of non-volatile resistive states in responseto some applied stimuli, within each individual array cell between twoor more resistive states. For example, each resistive state within aresistive change element cell can correspond to a data value which canbe programmed and read back by supporting circuitry within the device orarray.

For example, a resistive change element might be arranged to switchbetween two resistive states: a low resistive state (which mightcorrespond to a binary number 0) and a high resistive state (which mightcorrespond to a binary number 1). In this way, a resistive changeelement can be used to store one binary digit (bit) of data.

Or, as another example, a resistive change element might be arranged toswitch between four resistive states, so as to store two bits of data.Or a resistive change element might be arranged to switch between eightresistive states, so as to store three bits of data. Or a resistivechange element might be arranged to switch between 2^(n) resistivestates, so as to store n bits of data.

SUMMARY

The present disclosure provides a sense amplifier comprising a firstload device comprising a first plurality of field effect transistors, asecond load device comprising a second plurality of field effecttransistors where the second load device is in electrical communicationwith the first load device, a current source in electrical communicationwith the first load device and the second load device, a latch device, apower control device in electrical communication with the first loaddevice, the second load device, and the latch device, and the senseamplifier being configurable in an initializing configuration and acomparing configuration, where the first load device is configurable togenerate a first bias voltage in the initializing configuration and toset an operating point of a field effect transistor of the firstplurality of field effect transistors based on the first bias voltage inthe comparing configuration, and where the second load device isconfigurable to generate a second bias voltage in the initializingconfiguration and to set an operating point of a field effect transistorof the second plurality of field effect transistors based on the secondbias voltage in the comparing configuration.

According to another aspect of the present disclosure, the firstplurality of field effect transistors comprises a first plurality ofcapacitor connected PMOS transistors and the second plurality of fieldeffect transistors comprises a second plurality of capacitor connectedPMOS transistors.

According to another aspect of the present disclosure, the firstplurality of capacitor connected PMOS transistors are chargeable to thefirst bias voltage in the initializing configuration and the secondplurality of capacitor connected PMOS transistors are chargeable to thesecond bias voltage in the initializing configuration.

According to another aspect of the present disclosure, a capacitorconnected PMOS transistor of the first plurality of capacitor connectedPMOS transistors is in electrical communication with the second loaddevice and a capacitor connected PMOS transistor of the second pluralityof capacitor connected PMOS transistors is in electrical communicationwith the first load device.

According to another aspect of the present disclosure, the first loaddevice is configured to receive a first signal and a second signal, thesecond load device is configured to receive the first signal and thesecond signal, and the sense amplifier is configurable in theinitializing configuration and the comparing configuration based on thefirst signal and the second signal.

According to another aspect of the present disclosure, the senseamplifier further comprises a first input device in electricalcommunication with the first load device, where the first input deviceis configured to receive a first voltage, a second voltage, the firstsignal, and the second signal, where the first input device isconfigured to provide one of the first voltage and the second voltage tothe first load device based on the first signal and the second signal,and a second input device in electrical communication with the secondload device, where the second input device is configured to receive athird input voltage, the first signal, and the second signal, where thesecond input device is configured to provide the third voltage to thesecond load device based on the first signal and the second signal.

According to another aspect of the present disclosure, the first loaddevice is configured to receive a first voltage and the second loaddevice is configured to receive a second voltage.

According to another aspect of the present disclosure, the senseamplifier further comprises a first coupling canceller in electricalcommunication with the first load device and the second load device, anda second coupling canceller in electrical communication with the firstload device and the second load device.

According to another aspect of the present disclosure, the firstcoupling canceller comprises a capacitor connected NMOS transistor inelectrical communication with the first load device and the second loaddevice, and the second coupling canceller comprises a capacitorconnected NMOS transistor in electrical communication with the firstload device and the second load device.

According to another aspect of the present disclosure, the senseamplifier further comprises a first voltage swing limiter in electricalcommunication with the first load device and the second load device, asecond voltage swing limiter in electrical communication with the firstload device and the second load device, and the first voltage swinglimiter and the second voltage swing limiter are operable together tolimit a voltage difference between a voltage generated by the first loaddevice and a voltage generated by the second load device.

According to another aspect of the present disclosure, the first voltageswing limiter comprises a NMOS transistor having a drain terminal, agate terminal, and a source terminal, a PMOS transistor having a drainterminal, a gate terminal, and a source terminal, and where the gateterminal of the NMOS transistor is in electrical communication with thefirst load device and the gate terminal of the PMOS transistor, thesource terminal of the NMOS transistor is in electrical communicationwith the second load device and the source terminal of the PMOStransistor, and where the gate terminal of the PMOS transistor is inelectrical communication with the first load device and the gateterminal of the NMOS transistor, and the source terminal of the PMOStransistor is in electrical communication with the second load deviceand the source terminal of the NMOS transistor.

According to another aspect of the present disclosure, the secondvoltage swing limiter comprises a NMOS transistor having a drainterminal, a gate terminal, and a source terminal, a PMOS transistorhaving a drain terminal, a gate terminal, and a source terminal, andwhere the gate terminal of the NMOS transistor is in electricalcommunication with the second load device and the gate terminal of thePMOS transistor, the source terminal of the NMOS transistor is inelectrical communication with the first load device and the sourceterminal of the PMOS transistor, and where the gate terminal of the PMOStransistor is in electrical communication with the second load deviceand the gate terminal of the NMOS transistor, and the source terminal ofthe PMOS transistor is in electrical communication with the first loaddevice and the source terminal of the NMOS transistor.

According to another aspect of the present disclosure, the currentsource is configured to sink current.

The present disclosure provides a sense amplifier comprising a firstload device comprising a first plurality of field effect transistors, asecond load device comprising a second plurality of field effecttransistors where the second load device is in electrical communicationwith the first load device, a current source in electrical communicationwith the first load device and the second load device, a latch device, apower control device in electrical communication with the first loaddevice, the second load device, and the latch device, and the senseamplifier being configurable in an initializing configuration and acomparing configuration, where the first load device is configurable tocreate a current path through the first load device in the initializingconfiguration and to create a current path through the first load devicein the comparing configuration, where a first field effect transistor ofthe first plurality of field effect transistors is in the current paththrough the first load device in the initializing configuration and isin the current path through the first load device in the comparingconfiguration, where the first field effect transistor of the firstplurality of field effect transistors is configured to function as adiode in the initializing configuration and is configured to function asa resistor in the comparing configuration, where the second load deviceis configurable to create a current path through the second load devicein the initializing configuration and to create a current path throughthe second load device in the comparing configuration, where a firstfield effect transistor of the second plurality of field effecttransistors is in the current path through the second load device in theinitializing configuration and is in the current path through the secondload device in the comparing configuration, and where the first fieldeffect transistor of the second plurality of field effect transistors isconfigured to function as a diode in the initializing configuration andis configured to function as a resistor in the comparing configuration.

According to another aspect of the present disclosure, the first fieldeffect transistor of the first plurality of field effect transistors isa PMOS transistor and the first field effect transistor of the secondplurality of field effect transistors is a PMOS transistor.

According to another aspect of the present disclosure, a second fieldeffect transistor of the first plurality of field effect transistors isin the current path through the first load device in the initializingconfiguration and is in the current path through the first load devicein the comparing configuration and a second field effect transistor ofthe second plurality of field effect transistors is in the current paththrough the second load device in the initializing configuration and isin the current path through the second load device in the comparingconfiguration.

According to another aspect of the present disclosure, the second fieldeffect transistor of the first plurality of field effect transistors isa NMOS transistor and the second field effect transistor of the secondplurality of field effect transistors is a NMOS transistor.

According to another aspect of the present disclosure, the second fieldeffect transistor of the first plurality of field effect transistors isconfigured to function as a diode in the initializing configuration andthe second field effect transistor of the second plurality of fieldeffect transistors is configured to function as a diode in theinitializing configuration.

According to another aspect of the present disclosure, the firstplurality of field effect transistors comprises a capacitor connectedNMOS transistor, where the capacitor connected NMOS transistor of saidfirst plurality of field effect transistors is in electricalcommunication with the second field effect transistor of the firstplurality of field effect transistors, the second plurality of fieldeffect transistors comprises a capacitor connected NMOS transistor, andwhere the capacitor connected NMOS transistor of the second plurality offield effect transistors is in electrical communication with the secondfield effect transistor of the second plurality of field effecttransistors.

According to another aspect of the present disclosure, the firstplurality of field effect transistors comprises a first plurality ofcapacitor connected PMOS transistors and the second plurality of fieldeffect transistors comprises a second plurality of capacitor connectedPMOS transistors.

According to another aspect of the present disclosure, a capacitorconnected PMOS transistor of the first plurality of capacitor connectedPMOS transistors is in electrical communication with the second loaddevice and a capacitor connected PMOS transistor of the second pluralityof capacitor connected PMOS transistors is in electrical communicationwith the first load device.

According to another aspect of the present disclosure, the first loaddevice is configured to receive a first signal and a second signal, thesecond load device is configured to receive the first signal and thesecond signal, and the sense amplifier is configurable in theinitializing configuration and the comparing configuration based on thefirst signal and the second signal.

According to another aspect of the present disclosure, the senseamplifier further comprises a first input device in electricalcommunication with the first load device, where the first input deviceis configured to receive a first voltage, a second voltage, the firstsignal, and the second signal, where the first input device isconfigured to provide one of the first voltage and the second voltage tothe first load device based on the first signal and the second signal,and a second input device in electrical communication with the secondload device, where the second input device is configured to receive athird input voltage, the first signal, and the second signal, where thesecond input device is configured to provide the third voltage to thesecond load device based on the first signal and the second signal.

According to another aspect of the present disclosure, the first loaddevice is configured to receive a first voltage and the second loaddevice is configured to receive a second voltage.

According to another aspect of the present disclosure, the senseamplifier further comprises a first coupling canceller in electricalcommunication with the first load device and the second load device, anda second coupling canceller in electrical communication with the firstload device and the second load device.

According to another aspect of the present disclosure, the firstcoupling canceller comprises a capacitor connected NMOS transistor inelectrical communication with the first load device and the second loaddevice, and the second coupling canceller comprises a capacitorconnected NMOS transistor in electrical communication with the firstload device and the second load device.

According to another aspect of the present disclosure, the senseamplifier further comprises a first voltage swing limiter in electricalcommunication with the first load device and the second load device, asecond voltage swing limiter in electrical communication with the firstload device and the second load device, and the first voltage swinglimiter and the second voltage swing limiter are operable together tolimit a voltage difference between a voltage generated by the first loaddevice and a voltage generated by the second load device.

According to another aspect of the present disclosure, the first voltageswing limiter comprises a NMOS transistor having a drain terminal, agate terminal, and a source terminal, a PMOS transistor having a drainterminal, a gate terminal, and a source terminal, and where the gateterminal of the NMOS transistor is in electrical communication with thefirst load device and the gate terminal of the PMOS transistor, thesource terminal of the NMOS transistor is in electrical communicationwith the second load device and the source terminal of the PMOStransistor, and where the gate terminal of the PMOS transistor is inelectrical communication with the first load device and the gateterminal of the NMOS transistor and the source terminal of the PMOStransistor is in electrical communication with the second load deviceand the source terminal of the NMOS transistor.

According to another aspect of the present disclosure, the secondvoltage swing limiter comprises a NMOS transistor having a drainterminal, a gate terminal, and a source terminal, a PMOS transistorhaving a drain terminal, a gate terminal, and a source terminal, andwhere the gate terminal of the NMOS transistor is in electricalcommunication with the second load device and the gate terminal of thePMOS transistor, the source terminal of the NMOS transistor is inelectrical communication with the first load device and the sourceterminal of the PMOS transistor, and where the gate terminal of the PMOStransistor is in electrical communication with the second load deviceand the gate terminal of the NMOS transistor, and the source terminal ofthe PMOS transistor is in electrical communication with the first loaddevice and the source terminal of the NMOS transistor.

According to another aspect of the present disclosure, the currentsource is configured to sink current.

The present disclosure provides an electrical device comprising aresistive change element array comprising a plurality of resistivechange elements, a plurality of global bit lines for the resistivechange element array, a plurality of even bit lines for the resistivechange element array, a plurality of odd bit lines for the resistivechange element array, a plurality of word lines for the resistive changeelement array, a plurality of first selection devices where each firstselection device is in electrical communication with an even bit line ofthe plurality of even bit lines and a global bit line of the pluralityof global bit lines, a plurality of second selection devices where eachsecond selection device is in electrical communication with an odd bitline of the plurality of odd bit lines and a global bit line of theplurality of global bit lines, driver circuitry in electricalcommunication with the resistive change element array, and wheremultiple resistive change elements of the plurality of resistive changeelements are in electrical communication with the plurality of even bitlines and the plurality of word lines, and where plural resistive changeelements of the plurality of resistive change elements are in electricalcommunication with the plurality of odd bit lines and the plurality ofword lines.

According to another aspect of the present disclosure, the plurality offirst selection devices, the plurality of second selection devices, andthe driver circuitry are operable together to provide neutral voltageconditions for the plurality of resistive change elements.

According to another aspect of the present disclosure, the drivercircuitry is in electrical communication with the plurality of wordlines.

According to another aspect of the present disclosure, the plurality offirst selection devices are field effect transistors and the pluralityof second selection devices are field effect transistors.

According to another aspect of the present disclosure, the plurality offirst selection devices are NMOS transistors and the plurality of secondselection devices are NMOS transistors.

According to another aspect of the present disclosure, each resistivechange element of the plurality of resistive change elements has a firstelectrode, a second electrode, and a resistive change material betweenthe first electrode and the second electrode.

According to another aspect of the present disclosure, the resistivechange material comprises a nanotube fabric.

According to another aspect of the present disclosure, the electricaldevice further comprises a reference line, a reference line connectioncircuit in electrical communication with the reference line where thereference line connection circuit is configured to drive a voltage onthe reference line, a keeper circuit in electrical communication with aglobal bit line of the plurality of global bit lines where the keepercircuit is configured drive a voltage on the global bit line, at leastone bus line, a global bit line connection circuit in electricalcommunication with a global bit line of the plurality of global bitlines and a bus line of the at least one bus line where the global bitline connection circuit is configured to electrically connect the globalbit line and the bus line, at least one write buffer circuit inelectrical communication with the at least one bus line, at least onecurrent source in electrical communication with the at least one busline, and at least one sense device where each sense device of the atleast one sense device is in electrical communication with the referenceline and a bus line of the at least one bus line.

According to another aspect of the present disclosure, the referenceline connection circuit comprises a plurality of NMOS transistors andwhere each NMOS transistor of the plurality of NMOS transistors is inelectrical communication with the reference line.

According to another aspect of the present disclosure, the keepercircuit comprises a plurality of NMOS transistors and where each NMOStransistor of the plurality of NMOS transistors is in electricalcommunication with a global bit line of the plurality of global bitlines.

According to another aspect of the present disclosure, the global bitline connection circuit comprises a plurality of PMOS transistors andwhere each PMOS transistor of the plurality of PMOS transistors is inelectrical communication with a global bit line of the plurality ofglobal bit lines and a bus line of the at least one bus line.

According to another aspect of the present disclosure, each currentsource of the at least one current source is configurable to sink anamount of current for an operation of a resistive change element of theplurality of resistive change elements.

According to another aspect of the present disclosure, each sense deviceof the at least one sense device is a sense amplifier configurable intoan initializing configuration and a comparing configuration.

According to another aspect of the present disclosure, the electricaldevice further comprises a reference line, a reference line connectioncircuit in electrical communication with the reference line wherein thereference line connection circuit is configured to drive a voltage onthe reference line, a keeper circuit in electrical communication with aglobal bit line of the plurality of global bit lines where the keepercircuit is configured drive a voltage on the global bit line, at leastone bus line, at least one first input device in electricalcommunication with the at least one bus line, a second input device inelectrical communication with the reference line, a global bit lineconnection circuit in electrical communication with the reference line,a global bit line of the plurality of global bit lines, the second inputdevice, and a bus line of the at least one bus line where the global bitline connection circuit is configured to electrically connect thereference line and the second input device and where the global bit lineconnection circuit is configured to electrically connect the global bitline and the bus line, at least one write buffer circuit in electricalcommunication with the at least one bus line, at least one currentsource in electrical communication with the at least one bus line, andat least one sense device where each sense device of the at least onesense device is in electrical communication with a first input device ofthe at least one first input device and the second input device.

According to another aspect of the present disclosure, the global bitline connection circuit comprises a PMOS transistor in electricalcommunication with the reference line and the second input device, aplurality of PMOS transistors, and where each PMOS transistor of theplurality of PMOS transistors is in electrical communication with aglobal bit line of the plurality of global bit lines and a bus line theat least one bus line.

According to another aspect of the present disclosure, each sense deviceof the at least one sense device is a sense amplifier configurable intoan initializing configuration and a comparing configuration.

The present disclosure provides an electrical device comprising aplurality of global bit lines, a resistive change element array havingat least one section, driver circuitry for each section of the resistivechange element array where each section is in electrical communicationwith driver circuitry for that section, wherein each section comprises aplurality of even bit lines, a plurality of odd bit lines, a pluralityof word lines, a plurality of first selection devices where each firstselection device is in electrical communication with an even bit line ofthe plurality of even bit lines and a global bit line of the pluralityof global bit lines, a plurality of second selection devices where eachsecond selection device is in electrical communication with an odd bitline of the plurality odd bit lines and a global bit line of theplurality of global bit lines, and a plurality of resistive changeelements, where multiple resistive change elements of the plurality ofresistive change elements are in electrical communication with theplurality of even bit lines and the plurality of word lines, and whereinplural resistive change elements of the plurality of resistive changeelements are in electrical communication with the plurality of odd bitlines and the plurality of word lines.

According to another aspect of the present disclosure, the resistivechange element array and the driver circuitry for each section areoperable together to provide neutral voltage conditions.

According to another aspect of the present disclosure, the resistivechange element array has two sections.

According to another aspect of the present disclosure, the two sectionsof the resistive change element array have a same number of resistivechange elements.

According to another aspect of the present disclosure, the two sectionsof the resistive change element array have different numbers ofresistive change elements.

According to another aspect of the present disclosure, the resistivechange element array has three sections.

According to another aspect of the present disclosure, the plurality ofword lines of each section are in electrical communication with drivercircuitry for that section.

According to another aspect of the present disclosure, the plurality offirst selection devices are field effect transistors and the pluralityof second selection devices are field effect transistors.

According to another aspect of the present disclosure, the plurality offirst selection devices are NMOS transistors and the plurality of secondselection devices are NMOS transistors.

According to another aspect of the present disclosure, each resistivechange element of the plurality of resistive change elements has a firstelectrode, a second electrode, and a resistive change material betweenthe first electrode and the second electrode.

According to another aspect of the present disclosure, the resistivechange material comprises a nanotube fabric.

According to another aspect of the present disclosure, the electricaldevice further comprises a reference line, a reference line connectioncircuit for each section of the resistive change element array whereeach reference line connection circuit is in electrical communicationthe reference line and where each reference line connection circuit isconfigured to drive a voltage on the reference line, a keeper circuit inelectrical communication with a global bit line of the plurality ofglobal bit lines where the keeper circuit is configured drive a voltageon the global bit line, at least one bus line, a global bit lineconnection circuit in electrical communication with a global bit line ofthe plurality of global bit lines and a bus line of the at least one busline where the global bit line connection circuit is configured toelectrically connect the global bit line and the bus line, at least onewrite buffer circuit in electrical communication with the at least onebus line, at least one current source in electrical communication withthe at least one bus line, and at least one sense device where eachsense device of the at least one sense device is in electricalcommunication with the reference line and a bus line of the at least onebus line.

According to another aspect of the present disclosure, each referenceline connection circuit comprises a plurality of NMOS transistors andwhere each NMOS transistor of the plurality of NMOS transistors is inelectrical communication with the reference line.

According to another aspect of the present disclosure, the keepercircuit comprises a plurality of NMOS transistors and where each NMOStransistor of plurality of NMOS transistors is in electricalcommunication with a global bit line of the plurality of global bitlines.

According to another aspect of the present disclosure, the global bitline connection circuit comprises a plurality of PMOS transistors andwhere each PMOS transistor of the plurality of PMOS transistors is inelectrical communication with a global bit line of the plurality ofglobal bit lines and a bus line of the at least one bus line.

According to another aspect of the present disclosure, each currentsource of the at least one current source is configurable to sink anamount of current for an operation of a resistive change element of theplurality of resistive change elements.

According to another aspect of the present disclosure, each sense deviceof the at least one sense device is a sense amplifier configurable intoan initializing configuration and a comparing configuration.

According to another aspect of the present disclosure, the electricaldevice further comprises a reference line, a reference line connectioncircuit for each section of the resistive change element array whereineach reference line connection circuit is in electrical communicationwith the reference line and where each reference line connection circuitis configured to drive a voltage on the reference line, a keeper circuitin electrical communication with a global bit line of the plurality ofglobal bit lines, at least one bus line, at least one first input devicein electrical communication with the at least one bus line, a secondinput device in electrical communication with the reference line, aglobal bit line connection circuit in electrical communication with thereference line, a global bit line of the plurality of global bit lines,the second input device, and a bus line of the at least one bus linewhere the global bit line connection circuit is configured toelectrically connect the reference line and the second input device andwhere the global bit line connection circuit is configured toelectrically connect the global bit line and the bus line, at least onewrite buffer circuit in electrical communication with the at least onebus line, at least one current source in electrical communication withthe at least one bus line, and at least one sense device where eachsense device of the at least one sense device is in electricalcommunication with a first input device of the at least one first inputdevice and the second input device.

According to another aspect of the present disclosure, the global bitline connection circuit comprises a PMOS transistor in electricalcommunication with the reference line and the second input device, aplurality of PMOS transistors, and where each PMOS transistor of theplurality of PMOS transistors is in electrical communication with aglobal bit line of the plurality of global bit lines and a bus line theat least one bus line.

According to another aspect of the present disclosure, each sense deviceof the at least one sense device is a sense amplifier configurable intoan initializing configuration and a comparing configuration.

Other features and advantages of the present disclosure will becomeapparent from the following description, which is provided below inrelation to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A illustrates a simplified schematic diagram of a first exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 1B illustrates a simplified schematic diagram of an exemplary firstdriver circuit.

FIG. 1C illustrates a simplified schematic diagram of an exemplarysecond driver circuit.

FIG. 1D-1 illustrates a first part of a simplified schematic diagram ofan exemplary implementation of the first exemplary architecture forprogramming and accessing resistive change elements.

FIG. 1D-2 illustrates a second part of a simplified schematic diagram ofan exemplary implementation of the first exemplary architecture forprogramming and accessing resistive change elements.

FIG. 1E-1 illustrates a first part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during aPROGRAMMING operation to adjust a resistive state of resistive changeelement O01 to a low resistive state.

FIG. 1E-2 illustrates a second part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during aPROGRAMMING operation to adjust a resistive state of resistive changeelement O01 to a low resistive state.

FIG. 1F-1 illustrates a first part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during aPROGRAMMING operation to adjust a resistive state of resistive changeelement O01 to a high resistive state.

FIG. 1F-2 illustrates a second part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during aPROGRAMMING operation to adjust a resistive state of resistive changeelement O01 to a high resistive state.

FIG. 1G-1 illustrates a first part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during a READoperation of resistive change element O01 when resistive change elementO01 has a low resistive state.

FIG. 1G-2 illustrates a second part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during a READoperation of resistive change element O01 when resistive change elementO01 has a low resistive state.

FIG. 1H-1 illustrates a first part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during a READoperation of resistive change element O01 when resistive change elementO01 has a high resistive state.

FIG. 1H-2 illustrates a second part of a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through a resistive change element array during a READoperation of resistive change element O01 when resistive change elementO01 has a high resistive state.

FIG. 1I-1 illustrates a first part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the first exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 1I-2 illustrates a second part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the first exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 1I-3 illustrates a third part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the first exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 1J-1 illustrates a first part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a PROGRAMMING operation to adjust resistive states of oddresistive change elements in electrical communication with word lineWa(1) in Section A to low resistive states.

FIG. 1J-2 illustrates a second part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a PROGRAMMING operation to adjust resistive states of oddresistive change elements in electrical communication with word lineWa(1) in Section A to low resistive states.

FIG. 1J-3 illustrates a third part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a PROGRAMMING operation to adjust resistive states of oddresistive change elements in electrical communication with word lineWa(1) in Section A to low resistive states.

FIG. 1K-1 illustrates a first part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a PROGRAMMING operation to adjust resistive states of oddresistive change elements in electrical communication with word lineWa(1) in Section A to high resistive states.

FIG. 1K-2 illustrates a second part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a PROGRAMMING operation to adjust resistive states of oddresistive change elements in electrical communication with word lineWa(1) in Section A to high resistive states.

FIG. 1K-3 illustrates a third part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a PROGRAMMING operation to adjust resistive states of oddresistive change elements in electrical communication with word lineWa(1) in Section A to high resistive states.

FIG. 1L-1 illustrates a first part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 1L-2 illustrates a second part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 1L-3 illustrates a third part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the first exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 2A illustrates a simplified schematic diagram of a first senseamplifier.

FIG. 2B illustrates exemplary voltage waveforms for describing operationof the first sense amplifier of FIG. 2A for READ operations of resistivechange element O01, for describing operation of the second senseamplifier of FIG. 6 for READ operations of resistive change element O01,and for describing operation of the third sense amplifier of FIG. 7 forREAD operations of resistive change element O01.

FIG. 3 illustrates a flow chart showing a method for programming aresistive change element using neutral voltage conditions.

FIG. 4 illustrates a flow chart showing a method for accessing aresistive change element using neutral voltage conditions.

FIG. 5A illustrates a simplified schematic diagram of a second exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 5B-1 illustrates a first part of a simplified schematic diagram ofan exemplary implementation of the second exemplary architecture forprogramming and accessing resistive change elements.

FIG. 5B-2 illustrates a second part of a simplified schematic diagram ofan exemplary implementation of the second exemplary architecture forprogramming and accessing resistive change elements.

FIG. 5C illustrates a simplified schematic diagram of an exemplaryarrangement for two sense amplifiers sharing an input device.

FIG. 5D-1 illustrates a first part of a simplified schematic diagram ofthe exemplary implementation of FIGS. 5B-1 and 5B-2 showing current flowthrough a resistive change element array during a READ operation ofresistive change element O01 when resistive change element O01 has a lowresistive state.

FIG. 5D-2 illustrates a second part of a simplified schematic diagram ofthe exemplary implementation of FIGS. 5B-1 and 5B-2 showing current flowthrough a resistive change element array during a READ operation ofresistive change element O01 when resistive change element O01 has a lowresistive state.

FIG. 5E-1 illustrates a first part of a simplified schematic diagram ofthe exemplary implementation of FIGS. 5B-1 and 5B-2 showing current flowthrough a resistive change element array during a READ operation ofresistive change element O01 when resistive change element O01 has ahigh resistive state.

FIG. 5E-2 illustrates a second part of a simplified schematic diagram ofthe exemplary implementation of FIGS. 5B-1 and 5B-2 showing current flowthrough a resistive change element array during a READ operation ofresistive change element O01 when resistive change element O01 has ahigh resistive state.

FIG. 5F-1 illustrates a first part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the second exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 5F-2 illustrates a second part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the second exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 5F-3 illustrates a third part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the second exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 5F-4 illustrates a fourth part of a simplified schematic diagram ofan exemplary DDR compatible implementation of the second exemplaryarchitecture for programming and accessing resistive change elements.

FIG. 5G-1 illustrates a first part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the second exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 5G-2 illustrates a second part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the second exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 5G-3 illustrates a third part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the second exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 5G-4 illustrates a fourth part of a simplified schematic diagram ofthe exemplary DDR compatible implementation of the second exemplaryarchitecture showing current flow through a resistive change elementarray during a READ operation of odd resistive change elements inelectrical communication with word line Wa(1) in Section A.

FIG. 6 illustrates a simplified schematic diagram of a second senseamplifier.

FIG. 7 illustrates a simplified schematic diagram of a third senseamplifier.

DETAILED DESCRIPTION

The present disclosure provides circuit architectures for programmingand accessing resistive change elements. The circuit architectures ofthe present disclosure can program and access resistive change elementsusing neutral voltage conditions. The present disclosure also providesmethods for programming and accessing resistive change elements usingneutral voltage conditions. A neutral voltage condition is provided fora resistive change element in a resistive change element array byapplying a voltage to a top of the resistive change element and avoltage to a bottom of the resistive change element such that thosevoltages can reduce the magnitude and/or the number of voltagetransitions required for programming operations and accessingoperations. The voltages applied to the top and bottom of a resistivechange element to provide a neutral voltage condition may be the samevoltage or different voltages sufficient to provide a neutral voltagecondition. Suitable voltages for providing a neutral voltage conditionmay depend on voltages that are required for programming operations andaccessing operations, such as READ operations, SET VERIFY operations,and RESET VERIFY operations, and a voltage limit for disturbing aresistive state of a resistive change element.

For example, where a voltage of VDD (system voltage) is required to beapplied across a resistive change element for programming operations, avoltage of VDD is required to be applied to a top of a resistive changeelement for accessing operations, and a voltage limit for disturbing aresistive state of a resistive change element is greater than VDD/2(half the system voltage VDD), a neutral voltage condition can beprovided for the resistive change element by applying a voltage of VDD/2to a top of the resistive change element and a voltage of VDD/2 to abottom of the resistive change element. In the above example, providingneutral voltage conditions for resistive change elements in a resistivechange element array prior to applying voltages for programmingoperations reduces the magnitude of voltage transitions required forprogramming operations because a voltage transition of only VDD/2 isrequired to place a top of a resistive change element at a voltage ofVDD, and because a voltage transition of only negative VDD/2 is requiredto place a bottom of a resistive change element at a voltage of 0 voltsor ground. Also, in the above example, providing neutral voltageconditions prior to applying voltages for accessing operations reducesthe magnitude of voltage transitions required for accessing operationsbecause a voltage transition of only VDD/2 is required to place a top ofa resistive change element at a voltage of VDD. Additionally, in theabove example, providing neutral voltage conditions for resistive changeelements in a resistive change element array prior to applying voltagesfor programming operations and accessing operations reduces the numberof voltage transitions for programming operations and accessingoperations because only voltages on array lines in electricalcommunication with a resistive change element being programmed oraccessed are adjusted for programming and accessing operations, thevoltages on other array lines are not required to be adjusted so thatresistive states of other resistive change elements are not disturbed.It is noted that the terms bit line and word line are not limited to thelines designated below, but rather, the terms bit line and word line canbe used to refer to lines that differ from the designations below.

Voltages applied to a resistive change element to provide a neutralvoltage condition are design variables that can be selected by a circuitdesigner such that those voltages can reduce the magnitude and/or thenumber of voltage transitions required for programming operations andaccessing operations. It is noted that when voltages at the exactmidpoint between the system voltage VDD and 0 volts or ground areapplied to a resistive change element for a providing neutral voltagecondition, the voltage on a top of a resistive change element and thevoltage on a bottom of a resistive change element are adjusted by thesame voltage increment of VDD/2 to apply the system voltage VDD or toapply 0 volts or ground. It is further noted that although voltages atthe exact midpoint between the system voltage VDD and 0 volts or groundare discussed below as the exemplary voltages being applied to resistivechange elements for providing neutral voltage conditions, voltagesapplied to resistive change elements for providing neutral voltageconditions are not limited to being VDD/2 and a circuit designer canselect other voltages that may deviate somewhat from VDD/2 for providingneutral voltage conditions.

The present disclosure additionally provides sense amplifiersconfigurable into initializing configurations for initializing the senseamplifiers and comparing configurations for comparing voltages receivedby the sense amplifiers. The sense amplifiers can be initialized tocompensate for performance differences between parts of the senseamplifiers. For example, performance differences between parts of thesense amplifiers may be caused by manufacturing variations, fabricationvariations, temperature variations, and environment. Compensating forperformance differences between parts of the sense amplifiers canincrease accuracy of comparing voltages received by the senseamplifiers. Additionally, the sense amplifiers can be included in thecircuit architectures of the present disclosure and the sense amplifierscan increase accuracy of accessing operations, such as READ operations,SET VERIFY operations, and RESET VERIFY operations, by reducing errorsin determining resistive states of resistive change elements.

A PROGRAMMING operation of a resistive change element that isprogrammable into two non-volatile resistive states, a low resistivestate (corresponding, typically, to a logic 1, a SET state) and a highresistive state (corresponding, typically, to a logic 0, a RESET state),is an operation to adjust a resistive state of the resistive changeelement to a low resistive state or a high resistive state. A READoperation of a resistive change element that is programmable into twonon-volatile resistive states, a low resistive state (corresponding,typically, to a logic 1, a SET state) and a high resistive state(corresponding, typically, to a logic 0, a RESET state), is an operationto determine whether the resistive change element has a low resistivestate or a high resistive state. Additionally, a READ operation is usedto describe an operation where a resistive state of at least oneresistive change element is determined without significantly alteringthe resistive state. A SET VERIFY operation of a resistive changeelement that is programmable into two non-volatile resistive states, alow resistive state (corresponding, typically, to a logic 1, a SETstate) and a high resistive state (corresponding, typically, to a logic0, a RESET state), is an operation to determine whether the resistivechange element has a low resistive state or a resistive state other thana low resistive state. A SET VERIFY operation requires a correspondencebetween a resistance of a resistive change element and a modelresistance for a low resistive state to determine the resistive changeelement has a low resistive state closer than a correspondence between aresistance of a resistive change element and a model resistance for alow resistive state to determine the resistive change element has a lowresistive state for a READ operation. Additionally, a SET VERFIYoperation is used to describe an operation where it is determinedwhether a resistive state of at least one resistive change element is alow resistive state without significantly altering the resistive state.A RESET VERIFY operation of a resistive change element that isprogrammable into two non-volatile resistive states, a low resistivestate (corresponding, typically, to a logic 1, a SET state) and a highresistive state (corresponding, typically, to a logic 0, a RESET state),is an operation to determine whether the resistive change element has ahigh resistive state or a resistive state other than a high resistivestate. A RESET VERIFY operation requires a correspondence between aresistance of a resistive change element and a model resistance for ahigh resistive state to determine the resistive change element has ahigh resistive state closer than a correspondence between a resistanceof a resistive change element and a model resistance for a highresistive state to determine the resistive change element has a highresistive state for a READ operation. Additionally, a RESET VERFIYoperation is used to describe an operation where it is determinedwhether a resistive state of at least one resistive change element is ahigh resistive state without significantly altering the resistive state.

Referring now to FIG. 1A, a first exemplary architecture for programmingand accessing resistive change elements is illustrated in a simplifiedschematic diagram. The first exemplary architecture includes a resistivechange element array 100, a plurality of global bit lines GB1(0)-GB1(x),word line driver circuitry 101, a reference line RL1, a reference lineconnection circuit 102, a keeper circuit 103, a global bit lineconnection circuit 104, a bus line BL1, a write buffer circuit 105, acurrent source 106, a capacitor 107, and a sense device 108. It is notedthat although the first exemplary architecture is shown in FIG. 1Aincluding one bus line, one write buffer circuit, one current source,and one sense device, the first exemplary architecture can includemultiple bus lines, multiple write buffer circuits, multiple currentsources, and multiple sense devices. For example, the first exemplaryarchitecture can include multiple bus lines, multiple write buffercircuits, multiple current sources, and multiple sense devices so thatmultiple resistive change elements can be programmed to the sameresistive state at the same time and so that multiple resistive changeelements can be accessed at the same time. For example, to facilitatecompatibility with memory functionality where programming operationsprogram multiple bits of data at the same time and accessing operationsaccess multiple bits of data at the same time, such as double data rate(DDR) memory functionality, the first exemplary architecture can includeone bus line, one write buffer circuit, one current source, and onesense device for each global bit line in the plurality of global bitlines GB1(0)-GB1(x). In the above example where the first exemplaryarchitecture includes one bus line, one write buffer circuit, onecurrent source, one first input device, and one sense device for eachglobal bit line in the plurality of global bit lines GB1(0)-GB1(x), acircuit designer may select the number of global bit lines based on thenumber of bits of data to be accessed at the same time, such as 32global bit lines so that 32 bits of data can be accessed at the sametime and 64 global bit lines so that 64 bits of data can be accessed atthe same time.

Further, although the first exemplary architecture is shown in FIG. 1Aincluding a resistive change element array 100 having one section inelectrical communication with the plurality of global bit linesGB1(0)-GB1(x), the first exemplary architecture can include a resistivechange element array having multiple sections in electricalcommunication with the plurality of global bit lines GB1(0)-GB1(x) alongwith word line driver circuitry for each of the multiple sections and areference line connection circuit for each of the multiple sections. Forexample, the first exemplary architecture can include a resistive changeelement array having two sections in electrical communication with theplurality of global bit lines GB1(0)-GB1(x), word line driver circuitryfor each section and a reference line connection circuit for eachsection. In the above example, when the resistive change element arrayincludes two sections having the same number of resistive changeelements, the amount of data storage may be doubled as compared to aresistive change element array including one section having the samenumber of resistive change elements as one of the two sections withoutdoubling the chip area consumed by the first exemplary architecturebecause the keeper circuit 103, the global bit line connection circuit104, the bus line BL1, the write buffer circuit 105, the current source106, the capacitor 107, and the sense device 108 can be shared by thetwo sections. It is additionally noted that the chip area consumed bythe first exemplary architecture also can be reduced by locating wordline driver circuitry for each section and a reference line connectioncircuit for each section below the resistive change element array. It isfurther noted that the first exemplary architecture can include multiplebus lines, multiple write buffer circuits, multiple current sources,multiple sense devices, and a resistive change element array havingmultiple sections in electrical communication with the plurality ofglobal bit lines GB1(0)-GB1(x) and that the multiple bus lines, multiplewrite buffer circuits, multiple current sources, and multiple sensedevices can be shared by the multiple sections.

The resistive change element array 100 includes a plurality of resistivechange elements E00-Oxy, a plurality of even bit lines Be(0)-Be(x), aplurality of odd bit lines Bo(0)-Bo(x), a plurality of word linesW(0)-W(y), a plurality of even selection devices Ne0-Nex, and aplurality of odd selection devices No0-Nox. Each resistive changeelement in the plurality of resistive change elements E00-Oxy includes abottom electrode BE, a resistive change material, and a top electrodeTE. A nanotube fabric serves as the resistive change material. Theresistive change material is shown in FIG. 1A using diagonal linesbetween the bottom electrode BE and the top electrode TE. The bottomelectrode BE is in contact with the resistive change material and thetop electrode TE is in contact with the resistive change material.Alternatively, each resistive change element in the plurality ofresistive change elements E00-Oxy can include at least one interveninglayer located between the bottom electrode BE and the resistive changematerial, at least one intervening layer located between the resistivechange material and the top electrode TE, or at least one interveninglayer located between the bottom electrode BE and the resistive changematerial and at least one intervening layer located between theresistive change material and the top electrode TE. Alternatively, thebottom electrode BE can be omitted from each resistive change element inthe plurality of resistive change elements E00-Oxy, the top electrode TEcan be omitted from the each resistive change element in the pluralityof resistive change elements E00-Oxy, or the bottom electrode BE and thetop electrode TE can be omitted from each resistive change element inthe plurality of resistive change elements E00-Oxy. Alternatively, theresistive change material can comprise another resistive change materialsuch as other carbon allotropes such as Buckyballs, graphene flakes,nanocapsules, and nanohorns. It is noted that while the presentdisclosure provides some examples of resistive change elements includingnanotube fabrics or other carbon allotropes as resistive changematerials the present disclosure is not limited to resistive changeelements including nanotube fabrics or other carbon allotropes asresistive change materials and that the present disclosure is applicableto other types of resistive change elements such as phase change, metaloxide, and solid electrolyte.

Each resistive change element of the plurality of resistive changeelements E00-Oxy can be adjusted (programmed) between two non-volatileresistive states, a low resistive state, for example a resistance on theorder of 1MΩ (corresponding, typically, to a logic ‘1,’ a SET state),and a high resistive state, for example a resistance on the order of10MΩ (corresponding, typically, to a logic ‘0,’ a RESET state), byapplying electrical stimuli to the resistive change element. When theresistive change elements are adjusted (programmed) between resistivestates in a bidirectional manner, the resistive change elements areadjusted (programmed) between resistive states by electrical stimulithat cause current flow in different directions relative to the topelectrodes TE and the bottom electrodes BE. When the resistive changeelements are adjusted (programmed) between resistive states in abidirectional manner, the resistive change elements can be adjusted tothe low resistive state by an electrical stimulus that causes currentflow from the bottom electrode BE to the top electrode TE and can beadjusted to the high resistive state by an electrical stimulus thatcauses current flow from the top electrode TE to the bottom electrodeBE. When the resistive change elements are adjusted (programmed) betweenresistive states in a unidirectional manner, the resistive changeelements are adjusted (programmed) between resistive states byelectrical stimuli that cause current flow in the same directionrelative to the top electrodes TE and the bottom electrodes BE. When theresistive change elements are adjusted (programmed) between resistivestates in a unidirectional manner, the resistive change elements can beadjusted between the low resistive state and the high resistive state byelectrical stimuli that cause current flow in the same directionrelative to the top electrode TE and the bottom electrode BE.Alternatively, each resistive change element of the plurality ofresistive change elements E00-Oxy can be adjusted (programmed) betweenmore than two non-volatile resistive states, where each non-volatileresistive state corresponds with a different resistance value, byapplying electrical stimuli to the resistive change elements.

As shown in FIG. 1A, the even bit lines of the plurality of even bitlines Be(0)-Be(x) may be arranged generally along the Y-axis andgenerally in parallel with respect to each other, the odd bit lines ofthe plurality of odd bit lines Bo(0)-Bo(x) may be arranged generallyalong the Y-axis and generally in parallel with respect to each other,and the global bit lines of the plurality of global bit linesGB1(0)-GB1(x) may be arranged generally along the Y-axis and generallyin parallel with respect to each other. Also, as shown in FIG. 1A, theeven bit lines of the plurality of even bit lines Be(0)-Be(x), the oddbit lines of the plurality of odd bit lines Bo(0)-Bo(x), and the globalbit lines of the plurality of global bit lines GB1(0)-GB1(x) may bearranged generally in parallel with respect to each other. Additionally,as shown in FIG. 1A, the word lines of the plurality of word linesW(0)-W(y) may be arranged generally along the X-axis and generally inparallel with respect to each other. It is noted that the even bit linesBe(0)-Be(x) are described as being generally in parallel with respect toeach other, the odd bit lines Bo(0)-Bo(x) are described as beinggenerally in parallel with respect to each other, the global bit linesGB1(0)-GB1(x) are described as being generally in parallel with respectto each other, and the word lines W(0)-W(y) are described as beinggenerally in parallel with respect to each other to allow for variationsfrom exactly parallel due to the fabrication process. It is also notedthat the even bit lines Be(0)-Be(x), the odd bit lines Bo(0)-Bo(x), andthe global bit lines GB1(0)-GB1(x) are described as being generally inparallel with respect to each other to allow for variations from exactlyparallel due to the fabrication process.

The resistive change element array 100 has one even bit line and one oddbit line per column and one word line per row. The numbering conventionfor the plurality of even bit lines Be(0)-Be(x) and the plurality of oddbit lines Bo(0)-Bo(x) reflects that the resistive change element array100 has one even bit line and one odd bit line per column. The numberingconvention for the plurality of even bit lines Be(0)-Be(x) begins withthe letter B indicating the array line is a bit line followed by theletter e indicating the bit line is an even bit line followed by acolumn number in parentheses. The numbering convention for the pluralityof odd bit lines Bo(0)-Bo(x) begins with the letter B indicating thearray line is a bit line followed by the letter o indicating the bitline is an odd bit line followed by a column number in parentheses. Thenumbering convention for the plurality of word lines W(0)-W(y) beginswith the letter W indicating the array line is a word line followed by arow number in parentheses. The numbering convention for the plurality ofglobal bit lines GB1(0)-GB1(x) begins with letters and number GB1indicating the line is a global bit line followed by a column number inparentheses. Alternatively, the resistive change element array 100 mayhave at least one column with one even bit line and at least one columnwith one even bit line and one odd bit line, at least one column withone odd bit line and at least one column with one even bit line and oneodd bit line, or at least one column with one even bit line, at leastone column with one odd bit line, and at least one column with one evenbit line and one odd bit line. It is noted that for discussion purposesthe number 0 is considered to be an even number. Also, references to“even” and “odd” herein are for convenience of description and ease ofdistinction between groups of features and are not intended to be rigidcharacterizations, insofar as a same architecture could relabel the“even” structures as “odd” structures and vice versa.

As shown in FIG. 1A, the word lines of the plurality of word linesW(0)-W(y) may be generally orthogonal to the even bit lines of theplurality of even bit lines Be(0)-Be(x), the odd bit lines of theplurality of odd bit lines Bo(0)-Bo(x), and the global bit lines of theplurality of global bit lines GB1(0)-GB1(x). Additionally, as shown inFIG. 1A, the resistive change elements of the plurality of resistivechange elements E00-Oxy may be located where a word line of theplurality of word lines W(0)-W(y) crosses an even bit line of theplurality of even bit lines Be(0)-Be(x) and where a word line of theplurality of word lines W(0)-W(y) crosses an odd bit line of theplurality of odd bit lines Bo(0)-Bo(x). Resistive change elementslocated where a word line of the plurality of word lines W(0)-W(y)crosses an even bit line of the plurality of even bit lines Be(0)-Be(x)have top electrodes TE in electrical communication with word lines ofthe plurality of word lines W(0)-W(y) and bottom electrodes BE inelectrical communication with even bit lines of the plurality of evenbit lines Be(0)-Be(x). Resistive change elements located where a wordline of the plurality of word lines W(0)-W(y) crosses an odd bit line ofthe plurality of odd bit lines Bo(0)-Bo(x) have top electrodes TE inelectrical communication with word lines of the plurality of word linesW(0)-W(y) and bottom electrodes BE in electrical communication with oddbit lines of the plurality of odd bit lines Bo(0)-Bo(x).

The arrangement of the plurality of resistive change elements E00-Oxyreflects the resistive change element array 100 having one even bit lineand one odd bit line per column and one word line per row. As shown inFIG. 1A, the plurality of resistive change elements E00-Oxy is arrangedin a N×M matrix, where N is a positive integer that is a multiple of 2and M is a positive integer. The numbering convention for the pluralityof resistive change elements E00-Oxy includes the letter E indicatingthe resistive change element is in electrical communication with an evenbit line or the letter 0 indicating the resistive change element is inelectrical communication with an odd bit line followed by a columnnumber followed by a row number. It is noted that although FIG. 1A showsthe plurality of resistive change elements E00-Oxy arranged in arectangular matrix, the plurality of resistive change elements E00-Oxycan be arranged in other layouts such as a square matrix.

As shown in FIG. 1A, even bit lines of the plurality of even bit linesBe(0)-Be(x) and global bit lines of the plurality of global bit linesGB1(0)-GB1(x) having the same column number are in electricalcommunication with the same even selection device of the plurality ofeven selection devices Ne0-Nex. The plurality of even selection devicesNe0-Nex are n-channel metal oxide semiconductor field effecttransistors, also referred to as NMOS transistors, having drainterminals, gate terminals, and source terminals. The drain terminals ofthe plurality of even selection devices Ne0-Nex are in electricalcommunication with the plurality of global bit lines GB1(0)-GB1(x). Thegate terminals of the plurality of even selection devices Ne0-Nex are inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller. The source terminals of the pluralityof even selection devices Ne0-Nex are in electrical communication withthe plurality of even bit lines Be(0)-Be(x). The numbering conventionfor the plurality of even selection devices Ne0-Nex includes the lettere indicating the even selection device is in electrical communicationwith an even bit line followed by a column number. Alternatively, theeven selection devices Ne0-Nex can be other types of field effecttransistors, such as carbon nanotube field effect transistors (CNTFETs),SiGE FETs, fully-depleted silicon-on-insulator FETs, or multiple gatefield effect transistors such as FinFETs. It is noted that when fieldeffect transistors that do not require a semiconductor substrate areused this enables the field effect transistors to be fabricated oninsulator material, and additionally, enables the field effecttransistors to be stacked to reduce the amount of chip area consumed bythe plurality of even selection devices Ne0-Nex.

Also, as shown in FIG. 1A, odd bit lines of the plurality of odd bitlines Bo(0)-Bo(x) and global bit lines of the plurality of global bitlines GB1(0)-GB1(x) having the same column number are in electricalcommunication with the same odd selection device of the plurality of oddselection devices No0-Nox. The plurality of odd selection devicesNo0-Nox are n-channel metal oxide semiconductor field effecttransistors, also referred to as NMOS transistors, having drainterminals, gate terminals, and source terminals. The drain terminals ofthe plurality of odd selection devices No0-Nox are in electricalcommunication with the plurality of global bit lines GB1(0)-GB1(x). Thegate terminals of the plurality of odd selection devices No0-Nox are inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller. The source terminals of the pluralityof odd selection devices No0-Nox are in electrical communication withthe plurality of odd bit lines Bo(0)-Bo(x). The numbering convention forthe plurality of odd selection devices No0-Nox includes the letter oindicating the odd selection device is in electrical communication withan odd bit line followed by a column number. Alternatively, the oddselection devices No0-Nox can be other types of field effecttransistors, such as carbon nanotube field effect transistors (CNTFETs),SiGE FETs, fully-depleted silicon-on-insulator FETs, or multiple gatefield effect transistors such as FinFETs. It is noted that when fieldeffect transistors that do not require a semiconductor substrate areused this enables the field effect transistors to be fabricated oninsulator material, and additionally, enables the field effecttransistors to be stacked to reduce the amount of chip area consumed bythe plurality of odd selection devices No0-Nox.

The word line driver circuitry 101 is in electrical communication withthe plurality of word lines W(0)-W(y) and the word line driver circuitry101 is configured to drive voltages on the plurality of word linesW(0)-W(y) for programming operations, accessing operations, andproviding neutral voltage conditions. The word line driver circuitry 101can include a plurality of driver circuits with each driver circuitbeing a driver circuit such as the exemplary driver circuits discussedbelow with respect to FIGS. 1B-1C. Additionally, the word line drivercircuitry 101 can include word line driver circuitry such as theexemplary word line driver circuitry discussed below with respect toFIG. 1D-1. However, the word line driver circuitry 101 is not limited tothe driver circuits discussed below with respect to FIGS. 1B-1C and theword line driver circuitry discussed below with respect to FIG. 1D-1.For example, the word line driver circuitry 101 can include a pluralityof driver circuits with each driver circuit configured to drive avoltage on a word line of the plurality of word lines W(0)-W(y) forprogramming operations, accessing operations, and providing neutralvoltage conditions and each driver circuit being a driver circuit otherthan the exemplary driver circuits shown in FIGS. 1B-1C.

The reference line connection circuit 102 is in electrical communicationwith the reference line RL1 and the reference line connection circuit102 is configured to drive a voltage on the reference line RL1. Anexemplary circuit for the reference line connection circuit 102 isdiscussed below with respect to FIG. 1D-1. However, the reference lineconnection circuit 102 is not limited to the reference line connectioncircuit discussed below with respect to FIG. 1D-1. For example, thereference line connection circuit 102 can be other circuits configuredto drive the voltage on the reference line RL1.

The keeper circuit 103 is in electrical communication with the pluralityof global bit lines GB1(0)-GB1(x) and keeper circuit 103 is configuredto drive voltages on the plurality of global bit lines GB1(0)-GB1(x). Anexemplary circuit for the keeper circuit 103 is discussed below withrespect to FIG. 1D-2. However, the keeper circuit 103 is not limited tothe keeper circuit discussed below with respect to FIG. 1D-2. Forexample, the keeper circuit 103 can be other circuits configured todrive voltages on the plurality of global bit lines GB1(0)-GB1(x).

The global bit line connection circuit 104 is in electricalcommunication with the plurality of global bit lines GB1(0)-GB1(x) andthe bus line BL1 and the global bit line connection circuit 104 isconfigured to electrically connect the plurality of global bit linesGB1(0)-GB1(x) and the bus line BL1. An exemplary circuit for the globalbit line connection circuit 104 is discussed below with respect to FIG.1D-2. However, the global bit line connection circuit 104 is not limitedto the global bit line connection circuit discussed below with respectto FIG. 1D-2. For example, the global bit line connection circuit 104can be other circuits configured to electrically connect the pluralityof global bit lines GB1(0)-GB1(x) and the bus line BL1.

The write buffer circuit 105 is in electrical communication with the busline BL1 and the write buffer circuit 105 is configured to drivevoltages on the bus line BL1 and lines in electrical communication withthe bus line BL1 for programming operations. An exemplary circuit forthe write buffer circuit 105 is discussed below with respect to FIG.1D-2. However, the write buffer circuit 105 is not limited to the writebuffer circuit discussed below with respect to FIG. 1D-2. For example,the write buffer circuit 105 can be a circuit such as the exemplarydriver circuits discussed below with respect to FIGS. 1B-1C or otherdriver circuit.

The current source 106 is in electrical communication with the bus lineBL1. The current source 106 is configured to sink an amount of currentfor an operation of a resistive change element. The current source 106may be set to sink different amounts of current for different operationsof a resistive change element. For example, the current source 106 maybe set to sink an amount of current for a READ operation, an amount ofcurrent for a SET VERIFY operation, and an amount of current for a RESETVERIFY operation. Additionally, the current source 106 may be inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, and the current source 106 may be setto sink an amount of current based on at least one signal from thecontrol logic. Alternatively, the current source 106 may be hardwired tosink an amount of current.

The capacitor 107 has a first terminal and a second terminal. The firstterminal of the capacitor 107 is in electrical communication with thereference line RL1 and the second terminal of the capacitor 107 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The capacitor107 can reduce noise on the reference line RL1 by providing a path fornoise to flow to 0 volts or ground. Alternatively, the capacitor 107 canbe replaced with a plurality of capacitors, with each capacitor having afirst terminal in electrical communication with the reference line RL1and a second terminal in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies 0 voltsor ground. Alternatively, the capacitor 107 can be omitted.

The sense device 108 is in electrical communication with the referenceline RL1 and the bus line BL1 and the sense device 108 is configured togenerate at least one output voltage based on a voltage on the referenceline RL1 and a voltage on the bus line BL1. An exemplary sense amplifierfor the sense device 108 is discussed below with respect to FIGS. 1D-2and 2A. However, the sense device 108 is not limited to the senseamplifier discussed below with respect to FIGS. 1D-2 and 2A. Forexample, the sense device 108 can be a component that generates at leastone output voltage based on at least two input voltages, such as adifferential amplifier and a sense amplifiers other than the senseamplifier discussed below with respect to FIGS. 1D-2 and 2A.

FIG. 1B shows a simplified schematic diagram of an exemplary firstdriver circuit 109 a in electrical communication with a word line W1(0)of a resistive change element array represented by the word line W1(0),a bit line B1(0), and a resistive change element SW00 having a topelectrode TE in electrical communication with the word line W1(0), abottom electrode BE in electrical communication with the bit line B1(0),and a resistive change material between the top electrode TE and thebottom electrode BE. The first driver circuit 109 a includes aprogrammable voltage source 109 aa responsive to a control signal CNTRLsupplied by control logic such as a processor, a controller, and amicrocontroller. The control signal CNTRL can be based on a softwarealgorithm executed by the control logic. The programmable voltage source109 aa also provides a feedback signal CURRENT SENSE indicating thecurrent the programmable voltage source 109 aa is supplying duringoperation. The first driver circuit 109 a can also include additionalcomponents not shown in FIG. 1B, such a resistor for limiting currentflow from the programmable voltage source 109 aa. It is noted thatalthough the first driver circuit 109 a is shown in FIG. 1B inelectrical communication with the word line W1(0), the first drivercircuit 109 a can be in electrical communication with other lines, suchas bit lines, global bit lines, and bus lines, and can be used fordriving other lines, such as bit lines, global bit lines, and bus lines.

FIG. 1C shows a simplified schematic diagram of an exemplary seconddriver circuit 109 b in electrical communication with a word line W2(0)of a resistive change element array represented by the word line W2(0),a bit line B2(0), and a resistive change element SW00 having a topelectrode TE in electrical communication with the word line W2(0), abottom electrode BE in electrical communication with the bit line B2(0),and a resistive change material between the top electrode TE and thebottom electrode BE. The second driver circuit 109 b includes ap-channel metal oxide semiconductor field effect transistor 109 ba, alsoreferred to as a PMOS transistor, having a drain terminal, a gateterminal, and a source terminal, a first NMOS transistor 109 bb having adrain terminal, a gate terminal, and a source terminal, and a secondNMOS transistor 109 bc having a drain terminal, a gate terminal, and asource terminal. It is noted that although the second driver circuit 109b is shown in FIG. 1C in electrical communication with the word lineW2(0), the second driver circuit 109 b can be in electricalcommunication with other lines, such as bit lines, global bit lines, andbus lines, and can be used for driving other lines, such as bit lines,global bit lines, and bus lines. It is also noted that depending onvoltage levels being used, an NMOS transistor can be included in placeof the PMOS transistor 109 ba, a PMOS transistor can be included inplace of the first NMOS transistor 109 bb, and/or a PMOS transistor canbe included in place of the second NMOS transistor 109 bc. It is furthernoted that second driver circuit 109 b can include other types of fieldeffect transistors, such as carbon nanotube field effect transistors(CNTFETs), SiGe FETs, fully-depleted silicon-on-insulator FETs, ormultiple gate field effect transistors such as FinFETs, in place of thePMOS transistor 109 ba, the first NMOS transistor 109 bb, and/or thesecond NMOS transistor 109 bc.

The drain terminal of the PMOS transistor 109 ba is in electricalcommunication with the word line W2(0), the gate terminal of the PMOStransistor 109 ba is in electrical communication with a circuit, such asa control circuit, a decoder, a buffer, or a latch, that supplies asignal for controlling current flow through the PMOS transistor 109 ba,and the source terminal of the PMOS transistor 109 ba is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies a desired voltage. The drain terminal ofthe first NMOS transistor 109 bb is in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies a desired voltage, the gate terminal of the first NMOStransistor 109 bb is in electrical communication with a circuit, such asa control circuit, a decoder, a buffer, or a latch, that supplies asignal for controlling current flow through the first NMOS transistor109 bb, and the source terminal of the first NMOS transistor 109 bb isin electrical communication with the word line W2(0). The drain terminalof the second NMOS transistor 109 bc is in electrical communication withthe word line W2(0), the gate terminal of the second NMOS transistor 109bc is in electrical communication with a circuit, such as a controlcircuit, a decoder, a buffer, or a latch, that supplies a signal forcontrolling current flow through the second NMOS transistor 109 bc, andthe source terminal of the second NMOS transistor 109 bc is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. It is notedthat the second driver circuit 109 b can include additional componentsnot shown in FIG. 1C, such as at least one resistor for limiting currentflow and at least one additional field effect transistor in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies a desired voltage and the word line W2(0),and can omit components shown in FIG. 1C, such as the PMOS transistor109 ba, the first NMOS transistor 109 bb, and/or the second NMOStransistor 109 bc.

An exemplary implementation of the first exemplary architecture forprogramming and accessing resistive change elements is illustrated in asimplified schematic diagram in FIGS. 1D-1 and 1D-2. The exemplaryimplementation of the first exemplary architecture includes a pluralityof global bit lines GB2(0)-GB2(x), a resistive change element array 100,word line driver circuitry 110, a reference line RL2, a reference lineconnection circuit 120, a bus line BL2, a keeper circuit 130, a globalbit line connection circuit 140, a write buffer circuit 150, a currentsource 160, a capacitor 170, and a first sense amplifier 200. Theresistive change element array 100 and the plurality of global bit linesGB2(0)-GB2(x) have a similar structure to the resistive change elementarray 100 and the plurality of global bit lines GB1(0)-GB1(x) discussedabove with respect to the first exemplary architecture for programmingand accessing resistive change elements. Therefore, the resistive changeelement array 100 and the plurality of global bit lines GB2(0)-GB2(x)are not discussed in detail with respect to the exemplary implementationof the first exemplary architecture.

The word line driver circuitry 110 includes a first NMOS transistor 110p, a second NMOS transistor 111 p, a plurality of word line drivercircuits 110 d-11 yd, and a plurality of sink transistors 110 s-11 ys.The first NMOS transistor 110 p has a drain terminal, a gate terminal,and a source terminal, and the second NMOS transistor 111 p has a drainterminal, a gate terminal, and a source terminal. The drain terminal ofthe first NMOS transistor 110 p is in electrical communication with theplurality of word line driver circuits 110 d-11 yd, the gate terminal ofthe first NMOS transistor 110 p is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive a signal S0 for controlling current flow through the firstNMOS transistor 110 p, and the source terminal of the first NMOStransistor 110 p is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies thesystem voltage VDD. The drain terminal of the second NMOS transistor 111p is in electrical communication with the plurality of word line drivercircuits 110 d-11 yd and the reference line connection circuit 120, thegate terminal of the second NMOS transistor 111 p is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive a signal S1 for controlling current flowthrough the second NMOS transistor 111 p, and the source terminal of thesecond NMOS transistor 111 p is in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH.

Each word line driver circuit in the plurality of word line drivercircuits 110 d-11 yd has an input terminal, an output terminal, a firstpower terminal, and a second power terminal. The input terminals of theword line driver circuits in the plurality of word line driver circuits110 d-11 yd are in electrical communication with control logic, such asa processor, a controller, and a microcontroller. The output terminalsof the word line driver circuits in the plurality of word line drivercircuits 110 d-11 yd are in electrical communication with word lines inthe plurality of word lines W(0)-W(y) with the next to last referencecharacter for each word line driver circuit indicating the word linethat word line driver circuit is in electrical communication withbecause the next to last reference character for each word line drivercircuit refers to a row number. The first power terminals of the wordline driver circuits in the plurality of word line driver circuits 110d-11 yd are in electrical communication with the drain terminal of thefirst NMOS transistor 110 p. The second power terminals of the word linedriver circuits in the plurality of word line driver circuits 110 d-11yd are in electrical communication with the drain terminal of the secondNMOS transistor 111 p.

The plurality of word line driver circuits 110 d-11 yd receive aplurality of signals ITE0-ITEy for operating the plurality of word linedriver circuits 110 d-11 yd. The control logic supplies the plurality ofsignals ITE0-ITEy. The plurality of word line driver circuits 110 d-11yd receive the system voltage VDD on the first power terminals when thefirst NMOS transistor 110 p is turned on and do not receive a voltage onthe first power terminals when the first NMOS transistor 110 p is turnedoff. The plurality of word line driver circuits 110 d-11 yd receive theinhibit voltage VINH on the second power terminals when the second NMOStransistor 111 p is turned on and do not receive a voltage on the secondpower terminals when the second NMOS transistor 111 p is turned off.When the first NMOS transistor 110 p and the second NMOS transistor 111p are turned on each word line driver circuit in the plurality of wordline driver circuits 110 d-11 yd supplies a voltage based on the signalin the plurality of signals ITE0-ITEy received by that word line drivercircuit. For example, when the first NMOS transistor 110 p and thesecond NMOS transistor 111 p are turned on and the word line drivercircuit 110 d receives a signal ITE0 having a low level the word linedriver circuit 110 d supplies the system voltage VDD and when the firstNMOS transistor 110 p and the second NMOS transistor 111 p are turned onand the word line driver circuit 110 d receives a signal ITE0 having ahigh level the word line driver circuit 110 d supplies the inhibitvoltage VINH. When one of the first NMOS transistor 110 p and the secondNMOS transistor 111 p is turned on and one of the first NMOS transistor110 p and the second NMOS transistor 111 p is turned off each word linedriver circuit in the plurality of word line driver circuits 110 d-11 ydsupplies a voltage or does not supply a voltage based on the signal inthe plurality of signals ITE0-ITEy received by that word line drivercircuit. For example, when the first NMOS transistor 110 p is turned offand the second NMOS transistor 111 p is turned on and the word linedriver circuit 110 d receives a signal ITE0 having a low level the wordline driver circuit 110 d does not supply a voltage and when the firstNMOS transistor 110 p is turned off and the second NMOS transistor 111 pis turned on and the word line driver circuit 110 d receives a signalITE0 having a high level the word line driver circuit 110 d supplies theinhibit voltage VINH. It is noted that, as discussed below, the inhibitvoltage VINH is applied to a top of a resistive change element and theinhibit voltage VINH is applied to a bottom of the resistive changeelement to provide a neutral voltage condition. It is also noted thatthe inhibit voltage VINH can have a voltage level of VDD/2 (half of thesystem voltage VDD) for example, however, the inhibit voltage is notlimited to a voltage of VDD/2 and that a circuit designer can selectother voltages that may deviate somewhat from VDD/2 for the inhibitvoltage VINH.

The plurality of sink transistors 110 s-11 ys are NMOS transistorshaving drain terminals, gate terminals, and source terminals. The drainterminals of the plurality of sink transistors 110 s-11 ys are inelectrical communication with the plurality of word lines W(0)-W(y) withthe next to last reference character for each sink transistor indicatingthe word line that sink transistor is in electrical communication withbecause the next to last reference character for each sink transistorrefers to a row number. The gate terminals of the plurality of sinktransistors 110 s-11 ys are in electrical communication with controllogic, such as a processor, a controller, and a microcontroller. Thesource terminals of the plurality of sink transistors 110 s-11 ys are inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The pluralityof sink transistors 110 s-11 ys receive a plurality of signals SK0-SKyfor controlling current flow through the plurality of sink transistors110 s-11 ys. The control logic supplies the plurality of signalsSK0-SKy. Alternatively, the sink transistors 110 s-11 ys can be othertypes of field effect transistors, such as carbon nanotube field effecttransistors (CNTFETs), SiGE FETs, fully-depleted silicon-on-insulatorFETs, or multiple gate field effect transistors such as FinFETs. It isnoted that when field effect transistors that do not require asemiconductor substrate are used this enables the field effecttransistors to be fabricated on insulator material, and additionally,enables the field effect transistors to be stacked to reduce the amountof chip area consumed by the plurality of sink transistors 110 s-11 ys.

The reference line connection circuit 120 includes a first NMOStransistor 121 having a drain terminal, a gate terminal, and a sourceterminal and a second NMOS transistor 122 having a drain terminal, agate terminal, and a source terminal. The drain terminal of the firstNMOS transistor 121 is in electrical communication with the referenceline RL2, the gate terminal of the first NMOS transistor 121 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, and the source terminal of the firstNMOS transistor 121 is in electrical communication with the word linedriver circuitry 110. The drain terminal of the second NMOS transistor122 is in electrical communication with the reference line RL2, the gateterminal of the second NMOS transistor 122 is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, and the source terminal of the second NMOS transistor122 is in electrical communication with the word line driver circuitry110. The first NMOS transistor 121 receives a signal SSELe forcontrolling current flow through the first NMOS transistor 121 and theplurality of even selection devices Ne0-Nex. The second NMOS transistor122 receives a signal SSELo for controlling current flow through thesecond NMOS transistor 122 and the plurality of odd selection devicesNo0-Nox. The control logic supplies the signal SSELe and the signalSSELo. Alternatively, the source terminal of the first NMOS transistor121 and the source terminal of the second NMOS transistor 122 may be inelectrical communication a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH.Alternatively, the first NMOS transistor 121 and the second NMOStransistor 122 can be other types of field effect transistors, such ascarbon nanotube field effect transistors (CNTFETs), SiGE FETs,fully-depleted silicon-on-insulator FETs, or multiple gate field effecttransistors such as FinFETs. It is noted that when field effecttransistors that do not require a semiconductor substrate are used thisenables the field effect transistors to be fabricated on insulatormaterial, and additionally, enables the field effect transistors to bestacked to reduce the amount of chip area consumed by the first NMOStransistor 121 and the second NMOS transistor 122.

The keeper circuit 130 includes a plurality of NMOS transistors 130 k-13xk having drain terminals, gate terminals, and source terminals. Thedrain terminals of the plurality of NMOS transistors 130 k-13 xk are inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH. Thegate terminals of the plurality of NMOS transistors 130 k-13 xk are inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller. The source terminals of the pluralityof NMOS transistors 130 k-13 xk are in electrical communication with theplurality of global bit lines GB2(0)-GB2(x) with the next to lastreference character for each NMOS transistor indicating the global bitline that NMOS transistor is in electrical communication with becausethe next to last reference character for each NMOS transistor refers toa column number. The NMOS transistors in electrical communication withglobal bit lines having even column numbers receive a signal KEEPe forcontrolling current flow through the NMOS transistors in electricalcommunication with global bit lines having even column numbers. The NMOStransistors in electrical communication with the global bit lines havingodd column number receive a signal KEEPo for controlling current flowthrough the NMOS transistors in electrical communication with global bitlines having odd column numbers. The control logic supplies the signalKEEPe and the signal KEEPo. Alternatively, the drain terminals of theplurality of NMOS transistors 130 k-13 xk may be in electricalcommunication with a field effect transistor and the field effecttransistor may be in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies theinhibit voltage VINH. Alternatively, the plurality of NMOS transistors130 k-13 xk can be other types of field effect transistors, such ascarbon nanotube field effect transistors (CNTFETs), SiGE FETs,fully-depleted silicon-on-insulator FETs, or multiple gate field effecttransistors such as FinFETs. It is further noted that when field effecttransistors that do not require a semiconductor substrate are used thisenables the field effect transistors to be fabricated on insulatormaterial, and additionally, enables the field effect transistors to bestacked to reduce the amount of chip area consumed by the plurality ofNMOS transistors 130 k-13 xk.

The global bit line connection circuit 140 includes a plurality of PMOStransistors 140 g-14 xg having drain terminals, gate terminals, andsource terminals. The drain terminals of the plurality of PMOStransistors 140 g-14 xg are in electrical communication with the busline BL2. The gate terminals of the plurality of PMOS transistors 140g-14 xg are in electrical communication with control logic, such as aprocessor, a controller, and a microcontroller. The source terminals ofthe plurality of PMOS transistors 140 g-14 xg are in electricalcommunication with the plurality of global bit lines GB2(0)-GB2(x) withthe next to last reference character for each PMOS transistor indicatingthe global bit line that PMOS transistor is in electrical communicationwith because the next to last reference character refers to the columnnumber. The plurality of PMOS transistors 140 g-14 xg receive aplurality of signals YD0-YDx for controlling current flow through theplurality of PMOS transistors 140 g-14 xg. The control logic suppliesthe plurality of signals YD0-YDx. Alternatively, the PMOS transistors140 g-14 xg can be other types of field effect transistors, such ascarbon nanotube field effect transistors (CNTFETs), SiGE FETs,fully-depleted silicon-on-insulator FETs, or multiple gate field effecttransistors such as FinFETs. It is noted that when field effecttransistors that do not require a semiconductor substrate are used thisenables the field effect transistors to be fabricated on insulatormaterial, and additionally, enables the field effect transistors to bestacked to reduce the amount of chip area consumed by the plurality ofPMOS transistors 140 g-14 xg.

The write buffer circuit 150 has a first input terminal, a second inputterminal, an output terminal, a first power terminal, and a second powerterminal. The first input terminal and the second input terminal of thewrite buffer circuit 150 are in electrical communication with controllogic, such as a processor, a controller, and a microcontroller. Theoutput terminal of the write buffer circuit 150 is in electricalcommunication with bus line BL2. The first power terminal of the writebuffer circuit 150 is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies a systemvoltage VDD. The second power terminal of the write buffer circuit 150is in electrical communication with a power supply, a voltage source, adriver circuit, or other device that supplies 0 volts or ground. Thewrite buffer circuit 150 receives a write set signal WR0 on the firstinput terminal and a write reset signal WR1 on the second inputterminal. The control logic supplies the write set signal WR0 and thewrite reset signal WR1. When the write buffer circuit 150 receives thewrite set signal WR0 having a low level and the write reset signal WR1having a low level the write buffer circuit 150 supplies the systemvoltage VDD. When the write buffer circuit 150 receives the write setsignal WR0 having a high level and the write reset signal WR1 having ahigh level the write buffer circuit 150 supplies 0 volts or ground. Whenthe write buffer circuit 150 receives the write set signal WR0 having ahigh level and the write reset signal WR1 having a low level the writebuffer circuit 150 does not supply a voltage. Although, not shown inFIG. 1D-2, the output terminal of the write buffer circuit 150 may be inelectrical communication with the bus line BL2 through a resistor forlimiting current flow from the write buffer circuit 150. Alternatively,the first power terminal of the write buffer circuit 150 may be inelectrical communication with a field effect transistor and the fieldeffect transistor may be in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD and/or the second power terminal of thewrite buffer circuit 150 may be in electrical communication with a fieldeffect transistor and the field effect transistor may be in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies 0 volts or ground.

The current source 160 includes a first NMOS transistor 161 have a drainterminal, a gate terminal, and a source terminal and a second NMOStransistor 162 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 161 is inelectrical communication with the bus line BL2. The gate terminal of thefirst NMOS transistor 161 is in electrical communication with controllogic, such as a processor, a controller, and a microcontroller, toreceive a current source enable signal CSEN. The source terminal of thefirst NMOS transistor 161 is in electrical communication with the drainterminal of the second NMOS transistor 162. The drain terminal of thesecond NMOS transistor 162 is in electrical communication with thesource terminal of the first NMOS transistor 161. The gate terminal ofthe second NMOS transistor 162 is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive a current source bias current signal CSB. The source terminalof the second NMOS transistor 162 is in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies 0 volts or ground. The control logic supplies the currentsource enable signal CSEN to enable and disable the current source 160and the current source bias current signal CSB to set the amount ofcurrent sunk by the current source 160. The current source 160 may beset to sink different amounts of current for different operations of aresistive change element. For example, the current source 160 may be setto sink an amount of current for a READ operation, an amount of currentfor a SET VERIFY operation, and an amount of current for a RESET VERIFYoperation.

The capacitor 170 has a first terminal and a second terminal. The firstterminal of the capacitor 170 is in electrical communication with thereference line RL2 and the second terminal of the capacitor 170 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The capacitor170 can reduce noise on the reference line RL2 by providing a path fornoise to flow to 0 volts or ground. Alternatively, the capacitor 170 canbe replaced with a plurality of capacitors, with each capacitor having afirst terminal in electrical communication with the reference line RL2and a second terminal in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies 0 voltsor ground. Alternatively, the capacitor 170 can be omitted.

For ease of illustration, FIG. 1D-2 shows a simplified diagram of thefirst sense amplifier 200 having two input terminals in electricalcommunication with the reference line RL2, one input terminal inelectrical communication with bus line BL2, and two output terminals.The two output terminals can be in electrical communication with a bus,a buffer, a level shift circuit, a test circuit, or control logic suchas a processor, a controller, and a microcontroller. The first senseamplifier 200 is configurable into an initializing configuration and acomparing configuration. The first sense amplifier 200 is shown ingreater detail in a simplified schematic diagram in FIG. 2A and thefirst sense amplifier 200 is discussed in greater detail below.

The exemplary implementation of the first exemplary architecture shownin FIGS. 1D-1 and 1D-2 is discussed below with respect to PROGRAMMINGoperations, READ operations, SET VERIFY operations, and RESET VERIFYoperations. PROGRAMMING operations of resistive change elements in theexemplary implementation of FIGS. 1D-1 and 1D-2 are discussed below withrespect to FIGS. 1E-1 and 1E-2 that show current flow during aPROGRAMMING operation to adjust a resistive state of resistive changeelement O01 to a low resistive state and FIGS. 1F-1 and 1F-2 that showcurrent flow during a PROGRAMMING operation to adjust a resistive stateof resistive change element O01 to a high resistive state. READoperations, SET VERIFY operations, and RESET VERIFY operations ofresistive change elements in the exemplary implementation of the firstexemplary architecture shown in FIGS. 1D-1 and 1D-2 are discussed belowwith to respect FIGS. 1G-1 and 1G-2 that show current flow during a READoperation of resistive change element O01 when resistive change elementO01 has a low resistive state and FIGS. 1H-1 and 1H-2 that show currentflow during a READ operation of resistive change element O01 whenresistive change element O01 has a high resistive state. It is notedthat although PROGRAMMING operations, READ operations, SET VERIFYoperations, and RESET VERIFY operations of resistive change element O01in the exemplary implementation of the first exemplary architectureshown in FIGS. 1D-1 and 1D-2 will be explained in detail below,PROGRAMMING operations, READ operations, SET VERIFY operations, andRESET VERIFY operations of each resistive change element in theexemplary implementation of FIGS. 1D-1 and 1D-2 can be performed in asimilar manner to resistive change element O01.

FIG. 3 illustrates a flow chart 300 showing a method for programming aresistive change element using neutral voltage conditions. The methodstarts in step 302 with providing neutral voltage conditions for atleast one plurality of resistive change elements in a resistive changeelement array in an electrical device, where each resistive changeelement of the at least one plurality of resistive change elements is inelectrical communication with a bit line and a word line, and where eachresistive change element of the at least one plurality of resistivechange elements is adjustable between at least two resistive states. Themethod continues in step 304 with biasing a plurality of global bitlines. The method proceeds in step 306 with selecting at least oneresistive change element from the at least one plurality of resistivechange elements. The method continues in step 308 with preparing theelectrical device for applying an electrical stimulus to each of the atleast one resistive change element. The method proceeds in step 310 withapplying an electrical stimulus to each of the at least one resistivechange element to adjust a resistive state of each of the at least oneresistive change element. The method continues in step 312 withrestoring neutral voltage conditions for resistive change elementsimpacted by applying an electrical stimulus to each of the at least oneresistive change element. The method proceeds in step 314 with biasingglobal bit lines impacted by applying an electrical stimulus to each ofthe at least one resistive change element. It is noted that the steps ofthe method for programming a resistive change element using neutralvoltage conditions are not limited to being performed in the order shownin FIG. 3. For example, the steps of providing neutral voltageconditions for at least one plurality of resistive change elements in aresistive change element array in an electrical device and biasing aplurality of global bit lines can be performed at the same time. It isalso noted that the method for programming a resistive change elementusing neutral voltage conditions is not limited to the first exemplaryarchitecture and that the method for programming a resistive changeelement using neutral voltage conditions can be performed by otherarchitectures and systems. For example, the method for programming aresistive change element using neutral voltage conditions can beperformed by the second exemplary architecture shown in FIG. 5A. It isfurther noted that the method for programming a resistive change elementusing neutral voltage conditions can include additional steps.

Referring now to FIGS. 1E-1 and 1E-2, a PROGRAMMING operation to adjusta resistive state of the resistive change element O01 to a low resistivestate starts, as similarly discussed above in step 302 of the flow chart300, by providing neutral voltage conditions for the plurality ofresistive change elements E00-Oxy in the resistive change element array100. The neutral voltage conditions are provided for the plurality ofresistive change elements E00-Oxy by floating the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x) andapplying the inhibit voltage VINH to the plurality of word linesW(0)-W(y) with the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy. Floating a linerefers to electrically connecting the line such that a voltage on theline exists due to a line capacitance of the line. The plurality of evenbit lines Be(0)-Be(x) are floated by disconnecting the plurality of evenbit lines Be(0)-Be(x) from the plurality of global bit linesGB2(0)-GB2(x) by turning off the plurality of even selection devicesNe0-Nex. The plurality of even selection devices Ne0-Nex are turned offby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level. Theplurality of odd bit lines Bo(0)-Bo(x) are floated by disconnecting theplurality of odd bit lines Bo(0)-Bo(x) from the plurality of global bitlines GB2(0)-GB2(x) by turning off the plurality of odd selectiondevices No0-Nox. The plurality of odd selection devices No0-Nox areturned off by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a low level. It isnoted that control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level and asignal SSELo having a low level also turns off the first NMOS transistor121 and the second NMOS transistor 122 of the reference line connectioncircuit 120 and floats the reference line RL2.

The inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) by the word line driver circuitry 110 driving voltages on theplurality of word lines W(0)-W(y) to the inhibit voltage VINH. Theplurality of word line driver circuits 110 d-11 yd do not receive avoltage on the first power terminals because the first NMOS transistor110 p is turned off by control logic, such as a processor, a controller,and a microcontroller, supplying the signal S0 having a low level andreceive the inhibit voltage VINH on the second power terminals becausethe second NMOS transistor 111 p is turned on by the control logicsupplying the signal S1 having a high level. The plurality of word linedriver circuits 110 d-11 yd supply the inhibit voltage VINH based on theplurality of signals ITE0-ITEy supplied by control logic, such as aprocessor, a controller, and a microcontroller. The plurality of sinktransistors 110 s-11 ys are turned off because control logic, such as aprocessor, a controller, and a microcontroller, supplies the pluralityof signals SK0-SKy have low levels.

Driving voltages on the plurality of word lines W(0)-W(y) to the inhibitvoltage VINH with the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x) floating causes voltages on theplurality of word lines W(0)-W(y), voltages on the plurality of even bitlines Be(0)-Be(x), and voltages on the plurality of odd bit linesBo(0)-Bo(x) to be approximately equal to the inhibit voltage VINH.Voltages on the plurality of even bit lines Be(0)-Be(x) and voltages onthe plurality of odd bit lines Bo(0)-Bo(x) are approximately equal tothe inhibit voltage VINH because currents flow from the plurality ofword lines W(0)-W(y) through the plurality of resistive change elementsE00-Oxy into the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x). The inhibit voltage VINH existson the plurality of even bit lines Be(0)-Be(x) and the plurality of oddbit lines Bo(0)-Bo(x) due to line capacitances because the plurality ofeven bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) are floating. Thus, driving voltages on the plurality ofword lines W(0)-W(y) to the inhibit voltage VINH with the plurality ofeven bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) floating results in application of voltages approximatelyequal to the inhibit voltage VINH to the top electrodes and the bottomelectrodes of the resistive change elements in the plurality ofresistive change elements E00-Oxy. Additionally, driving voltages on theplurality of word lines W(0)-W(y) to the inhibit voltage VINH with theplurality of even bit lines Be(0)-Be(x) and the plurality of odd bitlines Bo(0)-Bo(x) floating causes the voltages across resistive changeelements in the plurality of resistive change elements E00-Oxy to beapproximately 0 volts.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a low resistive state continues, as similarlydiscussed above in step 304 of the flow chart 300, by biasing theplurality of global bit lines GB2(0)-GB2(x). The plurality of global bitlines GB2(0)-GB2(x) are biased to the inhibit voltage VINH by floatingthe plurality of global bit lines GB2(0)-GB2(x) and applying the inhibitvoltage VINH to the plurality of global bit lines GB2(0)-GB2(x). Theplurality of global bit lines GB2(0)-GB2(x) are floated by disconnectingthe plurality of global bit lines GB2(0)-GB2(x) from the plurality ofeven bit lines Be(0)-Be(x), the plurality of odd bit lines Bo(0)-Bo(x),and the bus line BL2. The plurality of global bit lines GB2(0)-GB2(x)may be disconnected from the plurality of even bit lines Be(0)-Be(x) andthe plurality of odd bit lines Bo(0)-Bo(x) as part of providing neutralvoltage conditions for the plurality of resistive change elementsE00-Oxy as discussed above. The plurality of global bit linesGB2(0)-GB2(x) are disconnected from the bus line BL2 by turning off theplurality of PMOS transistors 140 g-14 xg in the global bit lineconnection circuit 140. The plurality of PMOS transistors 140 g-14 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a plurality of signals YD0-YDx having highlevels. The inhibit voltage VINH is applied to the plurality of globalbit lines GB2(0)-GB2(x) by electrically connecting the plurality ofglobal bit lines GB2(0)-GB2(x) to a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHby turning on the plurality of NMOS transistors 130 k-13 xk in thekeeper circuit 130. The plurality of NMOS transistors 130 k-13 xk areturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a low resistive state proceeds, as similarlydiscussed above in step 306 of the flow chart 300, by selecting theresistive change element O01 from the plurality of resistive changeelements E00-Oxy. The resistive change element O01 is selected from theplurality of resistive change elements E00-Oxy by control logic, such asa processor, a controller, and a microcontroller. The resistive changeelements E00-Ox0, E01, Ex1-Ox1 and E0 y-Oxy in the plurality ofresistive change elements E00-Oxy that are not selected are referred toas unselected resistive change elements.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a low resistive state continues, as similarlydiscussed above in step 308 of the flow chart 300, by preparing theexemplary implementation of the first exemplary architecture forapplying an electrical stimulus to the resistive change element O01. Theexemplary implementation of the first exemplary architecture is preparedfor applying an electrical stimulus to the resistive change element O01by changing electrical connections of the odd bit line Bo(0), changingelectrical connections of the global bit line GB2(0), and disconnectinga power supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH from the global bit line GB2(0). Theelectrical connections of the odd bit line Bo(0) and the electricalconnections of the global bit line GB2(0) are changed and a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the global bitline GB2(0) so that the voltage on the odd bit line Bo(0) can be drivento a voltage for applying an electrical stimulus to the resistive changeelement O01. The electrical connections of the odd bit line Bo(0) arechanged so that the odd bit line Bo(0) is in electrical communicationwith the global bit line GB2(0). The odd bit line Bo(0) is electricallyconnected to the global bit line GB2(0) by turning on the odd selectiondevice No0. The odd selection device No0 is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying asignal SSELo having a high level. It is noted that the plurality of oddselection devices No0-Nox are turned on by the control logic supplying asignal SSELo having a high level, and thus, the plurality of odd bitlines Bo(0)-Bo(x) are electrically connected to the plurality of globalbit lines GB2(0)-GB2(x). It is also noted that the control logicsupplying a signal SSELo having a high level also turns on the secondNMOS transistor 122 of the reference line connection circuit 120 anddrives the voltage on the reference line RL2 to the inhibit voltage VINHby electrically connecting the reference line RL2 through the secondNMOS transistor 122 of the reference line connection circuit 120 and thesecond NMOS transistor 111 p of the word line driver circuitry 110 to apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH. It is further noted that, asdiscussed above with respect to providing neutral voltage conditions forthe plurality of resistive change elements E00-Oxy in the resistivechange element array 100, the second NMOS transistor 111 p of the wordline driver circuitry 110 is turned on.

The electrical connections of the global bit line GB2(0) are changed sothat the global bit line GB2(0) is in electrical communication with theodd bit line Bo(0) and the bus line BL2. The global bit line GB2(0) iselectrically connected to the odd bit line Bo(0) by turning on the oddselection device No0 as discussed above. The global bit line GB2(0) iselectrically connected to the bus line BL2 by turning on the PMOStransistor 140 g. The PMOS transistor 140 g is turned on by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal YD0 having a low level. A power supply, a voltagesource, a driver circuit, or other device that supplies the inhibitvoltage VINH is disconnected from the global bit line GB2(0) by turningoff the NMOS transistor 130 k. The NMOS transistor 130 k is turned offby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a low level. It isnoted that the control logic supplying a signal KEEPe having a low levelalso turns off NMOS transistors in the plurality of NMOS transistors 130k-13 xk in electrical communication with global bit lines having evencolumn numbers and disconnects global bit lines having even columnnumbers from a power supply, a voltage source, a driver circuit, orother device that supplies the inhibit voltage VINH.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a low resistive state proceeds, as similarlydiscussed above in step 310 of the flow chart 300, by applying anelectrical stimulus to the resistive change element O01 to adjust aresistive state of the resistive change element O01 to the low resistivestate. The electrical stimulus to adjust a resistive state of theresistive change element O01 to the low resistive state causes currentflow from the bottom electrode BE of the resistive change element O01 tothe top electrode TE of the resistive change element O01 and themagnitude of the voltage of the electrical stimulus is approximatelyequal to the system voltage VDD. As discussed above, providing neutralvoltage conditions for the plurality of resistive change elementsE00-Oxy causes voltages on the plurality of word lines W(0)-W(y),voltages on the plurality of even bit lines Be(0)-Be(x), and voltages onthe plurality of odd bit lines Bo(0)-Bo(x) to be approximately equal tothe inhibit voltage VINH. Also, as discussed above, the plurality ofglobal bit lines GB2(0)-GB2(x) are biased to the inhibit voltage VINH.Thus, the electrical stimulus to adjust a resistive state of theresistive change element O01 to the low resistive state is applied tothe resistive change element O01 by driving the voltage on the word lineW(1) from approximately the inhibit voltage VINH to 0 volts or groundand driving the voltage on the global bit line GB2(0) and the voltage onthe odd bit line Bo(0) from approximately the inhibit voltage VINH tothe system voltage VDD.

The voltage transition of the voltage on the word line W(1) generallycorresponds with the voltage transition of the voltage on the topelectrode TE of the resistive change element O01 because the voltage onthe word line W(1) generally corresponds with the voltage on the topelectrode TE of the resistive change element O01. The voltage transitionof the voltage on the odd bit line Bo(0) generally corresponds with thevoltage transition of the voltage on the bottom electrode BE of theresistive change element O01 because the voltage on the odd bit lineBo(0) generally corresponds with the voltage on the bottom electrode BEof the resistive change element O01. The magnitude of the voltagetransitions for applying the electrical stimulus to the resistive changeelement O01 to adjust a resistive state of the resistive change elementO01 to the low resistive state are reduced because the voltage appliedto the top electrode TE and the voltage applied to the bottom electrodeBE are not required to transition by the magnitude of the system voltageVDD. A voltage transition of 0 volts or ground minus the inhibit voltageVINH is required to place the top electrode at 0 volts or ground and avoltage transition of the system voltage VDD minus the inhibit voltageVINH is required to place the bottom electrode at the system voltageVDD. For example, when the inhibit voltage VINH is VDD/2 (half of thesystem voltage VDD), a voltage transition of 0 volts−VDD/2=−VDD/2 isrequired to place the top electrode at 0 volts or ground and a voltagetransition of VDD−VDD/2=VDD/2 is required to place the bottom electrodeat the system voltage VDD. Further, the number of voltage transitionsfor applying the electrical stimulus to adjust a resistive state of theresistive change element O01 to the low resistive state is reducedbecause only voltages on the word line W(1), the global bit line GB2(0),and the odd bit line Bo(0) are adjusted for applying the electricalstimulus to adjust a resistive state of the resistive change element O01to the low resistive state. It is noted that applying the inhibitvoltage VINH to a top electrode, a bottom electrode, or both a topelectrode and a bottom electrode of a resistive change element limits avoltage applied across a resistive change element to a voltage less thana voltage limit for disturbing a resistive state of a resistive changeelement while applying an electrical stimulus to the resistive changeelement 001 to adjust a resistive state of the resistive change elementO01 to the low resistive state.

The voltage on the word line W(1) is driven from the inhibit voltageVINH to 0 volts or ground by the word line driver circuit 111 d notsupplying a voltage and by electrically connecting the word line W(1) toa power supply, a voltage source, a driver circuit, or other device thatsupplies 0 volts or ground by turning on the sink transistor 111 s. Theword line driver circuit 111 d does not supply a voltage because theword line driver circuit 111 d is set to supply a voltage on the firstpower terminal based on the signal ITE1 supplied by control logic, suchas a processor, a controller, and a microcontroller, and the word linedriver circuit 111 d does not receive a voltage on the first powerterminal because the first NMOS transistor 110 p is turned off by thecontrol logic suppling the signal S0 having a low level. The sinktransistor 111 s is turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SK1 having a highlevel. The voltage on the global bit line GB2(0) and the voltage on theodd bit line Bo(0) are driven from the inhibit voltage VINH to thesystem voltage VDD by the write buffer circuit 150 supplying the systemvoltage VDD. The write buffer circuit 150 supplies the system voltageVDD based on the write set signal WR0 and the write reset signal WR1supplied by control logic, such as a processor, a controller, and amicrocontroller.

As shown in FIG. 1E-1, a current IO01 flows through the resistive changeelement O01 from the bottom electrode BE to the top electrode TE becausethe bottom electrode BE is at the system voltage VDD and the topelectrode TE is at 0 volts or ground. FIG. 1E-1 also shows leakagecurrents flowing through the resistive change elements O00, O0 y inelectrical communication with the odd bit line Bo(0) and leakagecurrents flowing through the resistive change elements E01, Ex1-Ox1 inelectrical communication with the word line W(1). The leakage currentsare shown using dashed lines in FIG. 1E-1. Leakage currents flow throughthe resistive change elements O00, O0 y because the bottom electrodes ofthe resistive change elements O00, O0 y are at the system voltage VDDand the top electrodes of the resistive change elements O00, O0 y arethe inhibit voltage VINH. Leakage currents flow through resistive changeelements E01, Ex1-Ox1 because the bottom electrodes of the resistivechange elements E01, Ex1-Ox1 are at the inhibit voltage VINH and the topelectrodes of the resistive change elements E01, Ex1-Ox1 are at 0 voltsor ground. It is noted that leakage currents may flow through resistivechange elements other than the resistive change elements in electricalcommunication with the odd bit line Bo(0) and the resistive changeelements in electrical communication with the word line W(1) becausevoltages on other lines may be impacted by applying the electricalstimulus to adjust a resistive state of the resistive change element O01to the low resistive state. It is also noted that leakage currents donot prevent the PROGRAMMING operation of the resistive change elementO01 when the leakage currents are much less than the amount of thecurrent IO01. It is further noted that the voltage differences acrossthe resistive change elements that cause the leakage currents do notdisturb the resistive states of the resistive change elements becausethe voltage differences are less than a voltage limit for disturbing aresistive state of a resistive change element.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a low resistive state proceeds, as similarlydiscussed above in step 312 of the flow chart 300, by restoring neutralvoltage conditions for resistive change elements impacted by applying anelectrical stimulus to the resistive change element O01. Neutral voltageconditions are restored for resistive change elements impacted byapplying the electrical stimulus to the resistive change element O01 byfloating the plurality of odd bit lines Bo(0)-Bo(x) and applying theinhibit voltage VINH to the word line W(1). The plurality of even bitlines Be(0)-Be(x) are already floating because the plurality of evenselection devices Ne0-Nex are turned off. The inhibit voltage VINH isalready applied to the word lines W(0), W(y) because the word linedriver circuits 110 d, 11 yd are already supplying the inhibit voltageVINH. The plurality of odd bit lines Bo(0)-Bo(x) are floated bydisconnecting the plurality of odd bit lines Bo(0)-Bo(x) from theplurality of global bit lines GB2(0)-GB2(x) by turning off the pluralityof odd selection devices No0-Nox. The plurality of odd selection devicesNo0-Nox are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELo having a lowlevel. The inhibit voltage VINH is applied to the word line W(1) byturning off the sink transistor 111 s and by the word line drivercircuit 111 d driving the voltage on the word line W(1) to the inhibitvoltage VINH. The sink transistor 111 s is turned off by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal SK1 having a low level. The word line driver circuit 111 dsupplies the inhibit voltage VINH based on the signal ITE1 supplied bycontrol logic, such as a processor, a controller, and a microcontroller.Thus, the inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) with the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a low resistive state continues, as similarlydiscussed above in step 314 of the flow chart 300, by biasing global bitlines impacted by applying an electrical stimulus to the resistivechange element O01. Global bit lines impacted by applying an electricalstimulus to the resistive change element O01 are biased to the inhibitvoltage VINH by floating the plurality of global bit lines GB2(0)-GB2(x)and applying the inhibit voltage VINH to global bit lines having evencolumn numbers. The plurality of global bit lines GB2(0)-GB2(x) arefloated by disconnecting the plurality of global bit lines GB2(0)-GB2(x)from the plurality of odd bit lines Bo(0)-Bo(x) and disconnecting theglobal bit line GB2(0) from the bus line BL2. The plurality of globalbit lines GB2(0)-GB2(x) are already disconnected from the plurality ofeven bit lines Be(0)-Be(x) because the plurality of even selectiondevices Ne0-Nex are turned off. The global bit lines other than globalbit line GB2(0) are already disconnected from the bus line BL2 becausethe PMOS transistors in the global bit line connection circuit 140 otherthan PMOS transistor 140 g are turned off. The plurality of global bitlines GB2(0)-GB2(x) may be disconnected from the plurality of odd bitlines Bo(0)-Bo(x) as part of restoring neutral voltage conditions forresistive change elements impacted by applying the electrical stimulusto the resistive change element O01 as discussed above. The global bitline GB2(0) is disconnected from the bus line BL2 by turning off thePMOS transistor 140 g. The PMOS transistor 140 g is turned off bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal YD0 having a high level. The inhibit voltage VINH isalready applied to the global bit lines having odd column numbersbecause the global bit lines having odd column numbers are in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the inhibit voltage VINH because the NMOStransistors 13 xk are turned on. The inhibit voltage VINH is applied tothe global bit lines having even column numbers by electricallyconnecting the global bit lines having even column numbers to a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH by turning on the NMOS transistors 130k. The NMOS transistors 130 k in electrical communication with theglobal bit lines having even column numbers are turned on by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal KEEPe having a high level.

Referring now to FIGS. 1F-1 and 1F-2, a PROGRAMMING operation to adjusta resistive state of the resistive change element O01 to a highresistive state starts, as similarly discussed above in step 302 of theflow chart 300, by providing neutral voltage conditions for theplurality of resistive change elements E00-Oxy in the resistive changeelement array 100. The neutral voltage conditions are provided for theplurality of resistive change elements E00-Oxy by floating the pluralityof even bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) and applying the inhibit voltage VINH to the plurality ofword lines W(0)-W(y) with the plurality of even bit lines Be(0)-Be(x)and the plurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy. Floating a linerefers to electrically connecting the line such that a voltage on theline exists due to a line capacitance of the line. The plurality of evenbit lines Be(0)-Be(x) are floated by disconnecting the plurality of evenbit lines Be(0)-Be(x) from the plurality of global bit linesGB2(0)-GB2(x) by turning off the plurality of even selection devicesNe0-Nex. The plurality of even selection devices Ne0-Nex are turned offby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level. Theplurality of odd bit lines Bo(0)-Bo(x) are floated by disconnecting theplurality of odd bit lines Bo(0)-Bo(x) from the plurality of global bitlines GB2(0)-GB2(x) by turning off the plurality of odd selectiondevices No0-Nox. The plurality of odd selection devices No0-Nox areturned off by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a low level. It isnoted that control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level and asignal SSELo having a low level also turns off the first NMOS transistor121 and the second NMOS transistor 122 of the reference line connectioncircuit 120 and floats the reference line RL2.

The inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) by the word line driver circuitry 110 driving voltages on theplurality of word lines W(0)-W(y) to the inhibit voltage VINH. Theplurality of word line driver circuits 110 d-11 yd receive the systemvoltage VDD on the first power terminals because the first NMOStransistor 110 p is turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying the signal S0 having a highlevel and receive the inhibit voltage VINH on the second power terminalsbecause the second NMOS transistor 111 p is turned on by the controllogic supplying the signal S1 having a high level. The plurality of wordline driver circuits 110 d-11 yd supply the inhibit voltage VINH basedon the plurality of signals ITE0-ITEy supplied by control logic, such asa processor, a controller, and a microcontroller. The plurality of sinktransistors 110 s-11 ys are turned off because control logic, such as aprocessor, a controller, and a microcontroller, supplies the pluralityof signals SK0-Sky having low levels.

Driving voltages on the plurality of word lines W(0)-W(y) to the inhibitvoltage VINH with the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x) floating causes voltages on theplurality of word lines W(0)-W(y), voltages on the plurality of even bitlines Be(0)-Be(x), and voltages on the plurality of odd bit linesBo(0)-Bo(x) to be approximately equal to the inhibit voltage VINH.Voltages on the plurality of even bit lines Be(0)-Be(x) and voltages onthe plurality of odd bit lines Bo(0)-Bo(x) are approximately equal tothe inhibit voltage VINH because currents flow from the plurality ofword lines W(0)-W(y) through the plurality of resistive change elementsE00-Oxy into the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x). The inhibit voltage VINH existson the plurality of even bit lines Be(0)-Be(x) and the plurality of oddbit lines Bo(0)-Bo(x) due to line capacitances because the plurality ofeven bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) are floating. Thus, driving voltages on the plurality ofword lines W(0)-W(y) to the inhibit voltage VINH with the plurality ofeven bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) floating results in application of voltages approximatelyequal to the inhibit voltage VINH to the top electrodes and the bottomelectrodes of the resistive change elements in the plurality ofresistive change elements E00-Oxy. Additionally, driving voltages on theplurality of word lines W(0)-W(y) to the inhibit voltage VINH with theplurality of even bit lines Be(0)-Be(x) and the plurality of odd bitlines Bo(0)-Bo(x) floating causes the voltages across resistive changeelements in the plurality of resistive change elements E00-Oxy to beapproximately 0 volts.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a high resistive state continues, as similarlydiscussed above in step 304 of the flow chart 300, by biasing theplurality of global bit lines GB2(0)-GB2(x). The plurality of global bitlines GB2(0)-GB2(x) are biased to the inhibit voltage VINH by floatingthe plurality of global bit lines GB2(0)-GB2(x) and applying the inhibitvoltage VINH to the plurality of global bit lines GB2(0)-GB2(x). Theplurality of global bit lines GB2(0)-GB2(x) are floated by disconnectingthe plurality of global bit lines GB2(0)-GB2(x) from the plurality ofeven bit lines Be(0)-Be(x), the plurality of odd bit lines Bo(0)-Bo(x),and the bus line BL2. The plurality of global bit lines GB2(0)-GB2(x)may be disconnected from the plurality of even bit lines Be(0)-Be(x) andthe plurality of odd bit lines Bo(0)-Bo(x) as part of providing neutralvoltage conditions for the plurality of resistive change elementsE00-Oxy as discussed above. The plurality of global bit linesGB2(0)-GB2(x) are disconnected from the bus line BL2 by turning off theplurality of PMOS transistors 140 g-14 xg in the global bit lineconnection circuit 140. The plurality of PMOS transistors 140 g-14 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a plurality of signals YD0-YDx having highlevels. The inhibit voltage VINH is applied to the plurality of globalbit lines GB2(0)-GB2(x) by electrically connecting the plurality ofglobal bit lines GB2(0)-GB2(x) to a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHby turning on the plurality of NMOS transistors 130 k-13 xk in thekeeper circuit 130. The plurality of NMOS transistors 130 k-13 xk areturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a high resistive state proceeds, as similarlydiscussed above in step 306 of the flow chart 300, by selecting theresistive change element O01 from the plurality of resistive changeelements E00-Oxy. The resistive change element O01 is selected from theplurality of resistive change elements E00-Oxy by control logic, such asa processor, a controller, and a microcontroller. The resistive changeelements E00-Ox0, E01, Ex1-Ox1 and E0 y-Oxy in the plurality ofresistive change elements E00-Oxy that are not selected are referred toas unselected resistive change elements.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a high resistive state continues, as similarlydiscussed above in step 308 of the flow chart 300, by preparing theexemplary implementation of the first exemplary architecture forapplying an electrical stimulus to the resistive change element O01. Theexemplary implementation of the first exemplary architecture is preparedfor applying an electrical stimulus to the resistive change element O01by changing electrical connections of the odd bit line Bo(0), changingelectrical connections of the global bit line GB2(0), and disconnectinga power supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH from the global bit line GB2(0). Theelectrical connections of the odd bit line Bo(0) and the electricalconnections of the global bit line GB2(0) are changed and a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the global bitline GB2(0) so that the voltage on the odd bit line Bo(0) can be drivento a voltage for applying an electrical stimulus to the resistive changeelement O01. The electrical connections of the odd bit line Bo(0) arechanged so that the odd bit line Bo(0) is in electrical communicationwith the global bit line GB2(0). The odd bit line Bo(0) is electricallyconnected to the global bit line GB2(0) by turning on the odd selectiondevice No0. The odd selection device No0 is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying asignal SSELo having a high level. It is noted that the plurality of oddselection devices No0-Nox are turned on by the control logic supplying asignal SSELo having a high level, and thus, the plurality of odd bitlines Bo(0)-Bo(x) are electrically connected to the plurality of globalbit lines GB2(0)-GB2(x). It is also noted that the control logicsupplying a signal SSELo having a high level also turns on the secondNMOS transistor 122 of the reference line connection circuit 120 anddrives the voltage on the reference line RL2 to the inhibit voltage VINHby electrically connecting the reference line RL2 through the secondNMOS transistor 122 of the reference line connection circuit 120 and thesecond NMOS transistor 111 p of the word line driver circuitry 110 to apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH. It is further noted that, asdiscussed above with respect to providing neutral voltage conditions forthe plurality of resistive change element E00-Oxy in the resistivechange element array 100, the second NMOS transistor 111 p of the wordline driver circuitry 110 is turned on.

The electrical connections of the global bit line GB2(0) are changed sothat the global bit line GB2(0) is in electrical communication with theodd bit line Bo(0) and the bus line BL2. The global bit line GB2(0) iselectrically connected to the odd bit line Bo(0) by turning on the oddselection device No0 as discussed above. The global bit line GB2(0) iselectrically connected to the bus line BL2 by turning on the PMOStransistor 140 g. The PMOS transistor 140 g is turned on by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal YD0 having a low level. A power supply, a voltagesource, a driver circuit, or other device that supplies the inhibitvoltage VINH is disconnected from the global bit line GB2(0) by turningoff the NMOS transistor 130 k. The NMOS transistor 130 k is turned offby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a low level. It isnoted that the control logic supplying a signal KEEPe having a low levelalso turns off NMOS transistors in the plurality of NMOS transistors 130k-13 xk in electrical communication with global bit lines having evencolumn numbers and disconnects global bit lines having even columnnumbers from a power supply, a voltage source, a driver circuit, orother device that supplies the inhibit voltage VINH.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a high resistive state proceeds, as similarlydiscussed above in step 310 of the flow chart 300, by applying anelectrical stimulus to the resistive change element O01 to adjust aresistive state of the resistive change element O01 to the highresistive state. The electrical stimulus to adjust a resistive state ofthe resistive change element O01 to the high resistive state causescurrent flow from the top electrode TE of the resistive change elementO01 to the bottom electrode BE of the resistive change element O01 andthe magnitude of the voltage of the electrical stimulus is approximatelyequal to the system voltage VDD. As discussed above, providing neutralvoltage conditions for the plurality of resistive change elementsE00-Oxy causes voltages on the plurality of word lines W(0)-W(y),voltages on the plurality of even bit lines Be(0)-Be(x), and voltages onthe plurality of odd bit lines Bo(0)-Bo(x) to be approximately equal tothe inhibit voltage VINH. Also, as discussed above, the plurality ofglobal bit lines GB2(0)-GB2(x) are biased to the inhibit voltage VINH.Thus, the electrical stimulus to adjust a resistive state of theresistive change element O01 to the high resistive state is applied tothe resistive change element O01 by driving the voltage on the word lineW(1) from approximately the inhibit voltage VINH to the system voltageVDD and driving the voltage on the global bit line GB2(0) and thevoltage on the odd bit line Bo(0) from approximately the inhibit voltageVINH to 0 volts or ground.

The voltage transition of the voltage on the word line W(1) generallycorresponds with the voltage transition of the voltage on the topelectrode TE of the resistive change element O01 because the voltage onthe word line W(1) generally corresponds with the voltage on the topelectrode TE of the resistive change element O01. The voltage transitionof the voltage on the odd bit line Bo(0) generally corresponds with thevoltage transition of the voltage on the bottom electrode BE of theresistive change element O01 because the voltage on the odd bit lineBo(0) generally corresponds with the voltage on the bottom electrode BEof the resistive change element O01. The magnitude of the voltagetransitions for applying the electrical stimulus to the resistive changeelement O01 to adjust a resistive state of the resistive change elementO01 to the high resistive state are reduced because the voltage appliedto the top electrode TE and the voltage applied to the bottom electrodeBE are not required to transition by the magnitude of the system voltageVDD. A voltage transition of the system voltage VDD minus the inhibitvoltage VINH is required to place the top electrode at the systemvoltage VDD and a voltage transition of 0 volts or ground minus theinhibit voltage VINH is required to place the bottom electrode at 0volts or ground. For example, when the inhibit voltage VINH is VDD/2(half of the system voltage VDD), a voltage transition ofVDD−VDD/2=VDD/2 is required to place the top electrode at the systemvoltage VDD and a voltage transition of 0 volts−VDD/2=−VDD/2 is requiredto place the bottom electrode at 0 volts or ground. Further, the numberof voltage transitions for applying the electrical stimulus to adjust aresistive state of the resistive change element O01 to the highresistive state is reduced because only voltages on the word line W(1),the global bit line GB2(0), and the odd bit line Bo(0) are adjusted forapplying the electrical stimulus to adjust a resistive state of theresistive change element O01 to the high resistive state. It is notedthat applying the inhibit voltage VINH to a top electrode, a bottomelectrode, or both a top electrode and a bottom electrode of a resistivechange element limits a voltage applied across a resistive changeelement to a voltage less than a voltage limit for disturbing aresistive state of a resistive change element while applying anelectrical stimulus to the resistive change element 001 to adjust aresistive state of the resistive change element O01 to the highresistive state.

The voltage on the word line W(1) is driven from the inhibit voltageVINH to the system voltage VDD by changing the voltage supplied by theword line driver circuit 111 d from the inhibit voltage VINH to thesystem voltage VDD. The word line driver circuit 111 d changes fromsupplying the inhibit voltage VINH to the system voltage VDD based on asignal ITE1 supplied by control logic, such as a processor, acontroller, and a microcontroller. The voltage on the global bit lineGB2(0) and the voltage on the odd bit line Bo(0) are driven from theinhibit voltage VINH to 0 volts or ground by the write buffer circuit150 supplying 0 volts or ground. The write buffer circuit 150 suppliesthe 0 volts or ground based on the write set signal WR0 and the writereset signal WR1 supplied by control logic, such as a processor, acontroller, and a microcontroller.

As shown in FIG. 1F-1, a current IO01 flows through the resistive changeelement O01 from the top electrode TE to the bottom electrode BE becausethe top electrode TE is at the system voltage VDD and the bottomelectrode BE is at 0 volts or ground. FIG. 1F-1 also shows leakagecurrents flowing through the resistive change elements O00, O0 y inelectrical communication with the odd bit line Bo(0) and leakagecurrents flowing through the resistive change elements E01, Ex1-Ox1 inelectrical communication with the word line W(1). The leakage currentsare shown using dashed lines in FIG. 1F-1. Leakage currents flow throughthe resistive change elements O00, O0 y because the top electrodes ofthe resistive change elements O00, O0 y are at the inhibit voltage andthe bottom electrodes of the resistive change elements O00, O0 y are 0volts or ground. Leakage currents flow through resistive change elementsE01, Ex1-Ox1 because the top electrodes of the resistive change elementsE01, Ex1-Ox1 are at the system voltage VDD and the bottom electrodes ofthe resistive change elements E01, Ex1-Ox1 are at inhibit voltage VINH.It is noted that leakage currents may flow through resistive changeelements other than the resistive change elements in electricalcommunication with the odd bit line Bo(0) and the resistive changeelements in electrical communication with the word line W(1) becausevoltages on other lines may be impacted by applying the electricalstimulus to adjust a resistive state of the resistive change element O01to the high resistive state. It is also noted that leakage currents donot prevent the PROGRAMMING operation of the resistive change elementO01 when the leakage currents are much less than the amount of thecurrent 1001. It is further noted that the voltage differences acrossthe resistive change elements that cause the leakage currents do notdisturb the resistive states of the resistive change elements becausethe voltage difference are less than a voltage limit for disturbing aresistive state of a resistive change element.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a high resistive state proceeds, as similarlydiscussed above in step 312 of the flow chart 300, by restoring neutralvoltage conditions for resistive change elements impacted by applying anelectrical stimulus to the resistive change element O01. Neutral voltageconditions are restored for resistive change elements impacted byapplying the electrical stimulus to the resistive change element O01 byfloating the plurality of odd bit lines Bo(0)-Bo(x) and applying theinhibit voltage VINH to the word line W(1). The plurality of even bitlines Be(0)-Be(x) are already floating because the plurality of evenselection devices Ne0-Nex are turned off. The inhibit voltage VINH isalready applied to the word lines W(0), W(y) because the word linedriver circuits 110 d, 11 yd are already supplying the inhibit voltageVINH. The plurality of odd bit lines Bo(0)-Bo(x) are floated bydisconnecting the plurality of odd bit lines Bo(0)-Bo(x) from theplurality of global bit lines GB2(0)-GB2(x) by turning off the pluralityof odd selection devices No0-Nox. The plurality of odd selection devicesNo0-Nox are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELo having a lowlevel. The inhibit voltage VINH is applied to the word line W(1) bychanging the voltage supplied by the word line driver circuit 111 d fromthe system voltage VDD to the inhibit voltage VINH. The word line drivercircuit 111 d changes from supplying the system voltage VDD to theinhibit voltage VINH based on a signal ITE1 supplied by control logic,such as a processor, a controller, and a microcontroller. Thus, theinhibit voltage VINH is applied to the plurality of word lines W(0)-W(y)with the plurality of even bit lines Be(0)-Be(x) and the plurality ofodd bit lines Bo(0)-Bo(x) floating so that voltages approximately equalto the inhibit voltage VINH are applied to the top electrodes and thebottom electrodes of the resistive change elements in the plurality ofresistive change elements E00-Oxy.

The PROGRAMMING operation to adjust a resistive state of the resistivechange element O01 to a high resistive state continues, as similarlydiscussed above in step 314 of the flow chart 300, by biasing global bitlines impacted by applying an electrical stimulus to the resistivechange element O01. Global bit lines impacted by applying an electricalstimulus to the resistive change element O01 are biased to the inhibitvoltage VINH by floating the plurality of global bit lines GB2(0)-GB2(x)and applying the inhibit voltage VINH to global bit lines having evencolumn numbers. The plurality of global bit lines GB2(0)-GB2(x) arefloated by disconnecting the plurality of global bit lines GB2(0)-GB2(x)from the plurality of odd bit lines Bo(0)-Bo(x) and disconnecting theglobal bit line GB2(0) from the bus line BL2. The plurality of globalbit lines GB2(0)-GB2(x) are already disconnected from the plurality ofeven bit lines Be(0)-Be(x) because the plurality of even selectiondevices Ne0-Nex are turned off. The global bit lines other than globalbit line GB2(0) are already disconnected from the bus line BL2 becausethe PMOS transistors in the global bit line connection circuit 140 otherthan PMOS transistor 140 g are turned off. The plurality of global bitlines GB2(0)-GB2(x) may be disconnected from the plurality of odd bitlines Bo(0)-Bo(x) as part of restoring neutral voltage conditions forresistive change elements impacted by applying the electrical stimulusto the resistive change element O01 as discussed above. The global bitline GB2(0) is disconnected from the bus line BL2 by turning off thePMOS transistor 140 g. The PMOS transistor 140 g is turned off bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal YD0 having a high level. The inhibit voltage VINH isalready applied to the global bit lines having odd column numbersbecause the global bit lines having odd column numbers are in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the inhibit voltage VINH because the NMOStransistors 13 xk are turned on. The inhibit voltage VINH is applied tothe global bit lines having even column numbers by electricallyconnecting the global bit lines having even column numbers to a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH by turning on the NMOS transistors 130k. The NMOS transistors 130 k in electrical communication with theglobal bit lines having even column numbers are turned on by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal KEEPe having a high level.

FIG. 4 illustrates a flow chart 400 showing a method for accessingresistive change elements using neutral voltage conditions. The methodstarts in step 402 with providing neutral voltage conditions for atleast one plurality of resistive change elements in a resistive changeelement array in an electrical device, where each resistive changeelement of the at least one plurality of resistive change elements is inelectrical communication with a bit line and a word line, and where eachresistive change element of the at least one plurality of resistivechange elements is adjustable between at least two resistive states. Themethod continues in step 404 with biasing a plurality of global bitlines. The method proceeds in step 406 with selecting at least oneresistive change element from the at least one plurality of resistivechange elements. The method continues in step 408 with preparing theelectrical device for determining a resistive state of each of the atleast one resistive change element. The method proceeds in step 410 withgenerating a voltage indicative of a resistive state for each of the atleast one resistive change element. The method continues in step 412with determining a resistive state based on a voltage indicative of aresistive state for that resistive change element for each of the atleast one resistive change element. The method proceeds in step 414 withrestoring neutral voltage conditions for resistive change elementsimpacted by generating a voltage indicative of a resistive state foreach of the at least one resistive change element. The method continuesin step 416 with biasing global bit lines impacted by generating avoltage indicative of a resistive state for each of the at least oneresistive change element. It is noted that the steps of the method foraccessing a resistive change element using neutral voltage conditionsare not limited to being performed in the order shown in FIG. 4. Forexample, the steps of providing neutral voltage conditions for at leastone plurality of resistive change elements in a resistive change elementarray in an electrical device and biasing a plurality of global bitlines can be performed at the same time. It is also noted that themethod for accessing a resistive change element using neutral voltageconditions is not limited to the first exemplary architecture and thatthe method for accessing a resistive change element using neutralvoltage conditions can be performed by other architectures and systems.For example, the method for accessing a resistive change element usingneutral voltage conditions can be performed by the second exemplaryarchitecture shown in FIG. 5A. It is further noted that the method foraccessing a resistive change element using neutral voltage conditionscan include additional steps, such as selecting an amount of current forgenerating a voltage indicative of a resistive state of the resistivechange element. It is additionally noted that READ operations, SETVERIFY operations, and RESET VERIFY operations generally use differentamounts of current for generating a voltage indicative of a resistivestate of a resistive change element because READ operations, SET VERIFYoperations, and RESET VERIFY operation make different determinations.

Referring now to FIGS. 1G-1 and 1G-2, a READ operation of the resistivechange element O01 starts, as similarly discussed above in step 402 ofthe flow chart 400, by providing neutral voltage conditions for theplurality of resistive change elements E00-Oxy in the resistive changeelement array 100. The neutral voltage conditions are provided for theplurality of resistive change elements E00-Oxy by floating the pluralityof even bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) and applying the inhibit voltage VINH to the plurality ofword lines W(0)-W(y) with the plurality of even bit lines Be(0)-Be(x)and the plurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy. Floating a linerefers to electrically connecting the line such that a voltage on theline exists due to a line capacitance of the line. The plurality of evenbit lines Be(0)-Be(x) are floated by disconnecting the plurality of evenbit lines Be(0)-Be(x) from the plurality of global bit linesGB2(0)-GB2(x) by turning off the plurality of even selection devicesNe0-Nex. The plurality of even selection devices Ne0-Nex are turned offby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level. Theplurality of odd bit lines Bo(0)-Bo(x) are floated by disconnecting theplurality of odd bit lines Bo(0)-Bo(x) from the plurality of global bitlines GB2(0)-GB2(x) by turning off the plurality of odd selectiondevices No0-Nox. The plurality of odd selection devices No0-Nox areturned off by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a low level. It isnoted that control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level and asignal SSELo having a low level also turns off the first NMOS transistor121 and the second NMOS transistor 122 of the reference line connectioncircuit 120 and floats the reference line RL2.

The inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) by the word line driver circuitry 110 driving voltages on theplurality of word lines W(0)-W(y) to the inhibit voltage VINH. Theplurality of word line driver circuits 110 d-11 yd receive the systemvoltage VDD on the first power terminals because the first NMOStransistor 110 p is turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying the signal S0 having a highlevel and receive the inhibit voltage VINH on the second power terminalsbecause the second NMOS transistor 111 p is turned on by the controllogic supplying the signal S1 having a high level. The plurality of wordline driver circuits 110 d-11 yd supply the inhibit voltage VINH basedon the plurality of signals ITE0-ITEy supplied by control logic, such asa processor, a controller, and a microcontroller. The plurality of sinktransistors 110 s-11 ys are turned off because control logic, such as aprocessor, a controller, and a microcontroller, supplies the pluralityof signal SK0-Sky having low levels.

Driving the plurality of word lines W(0)-W(y) to the inhibit voltageVINH with the plurality of even bit lines Be(0)-Be(x) and the pluralityof odd bit lines Bo(0)-Bo(x) floating causes voltages on the pluralityof word lines W(0)-W(y), voltages on the plurality of even bit linesBe(0)-Be(x), and voltages on the plurality of odd bit lines Bo(0)-Bo(x)to be approximately equal to the inhibit voltage VINH. Voltages on theplurality of even bit lines Be(0)-Be(x) and voltages on the plurality ofodd bit lines Bo(0)-Bo(x) are approximately equal to the inhibit voltageVINH because currents flow from the plurality of word lines W(0)-W(y)through the plurality of resistive change elements E00-Oxy into theplurality of even bit lines Be(0)-Be(x) and the plurality of odd bitlines Bo(0)-Bo(x). The inhibit voltage VINH exists on the plurality ofeven bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) due to line capacitances because the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x) arefloating. Thus, driving voltages on the plurality of word linesW(0)-W(y) to the inhibit voltage VINH with the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x)floating results in application of voltages approximately equal to theinhibit voltage VINH to the top electrodes and the bottom electrodes ofthe resistive change elements in the plurality of resistive changeelements E00-Oxy. Additionally, driving the plurality of word linesW(0)-W(y) to the inhibit voltage VINH with the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00-Oxy to be approximately 0volts.

The READ operation of the resistive change element O01 continues, assimilarly discussed above in step 404 of the flow chart 400, by biasingthe plurality of global bit lines GB2(0)-GB2(x). The plurality of globalbit lines GB2(0)-GB2(x) are biased to the inhibit voltage VINH byfloating the plurality of global bit lines GB2(0)-GB2(x) and applyingthe inhibit voltage VINH to the plurality of global bit linesGB2(0)-GB2(x). The plurality of global bit lines GB2(0)-GB2(x) arefloated by disconnecting the plurality of global bit lines GB2(0)-GB2(x)from the plurality of even bit lines Be(0)-Be(x), the plurality of oddbit lines Bo(0)-Bo(x), and the bus line BL2. The plurality of global bitlines GB2(0)-GB2(x) may be disconnected from the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x) as partof providing neutral voltage conditions for the plurality of resistivechange elements E00-Oxy as discussed above. The plurality of global bitlines GB2(0)-GB2(x) are disconnected from the bus line BL2 by turningoff the plurality of PMOS transistors 140 g-14 xg in the global bit lineconnection circuit 140. The plurality of PMOS transistors 140 g-14 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a plurality of signals YD0-YDx having highlevels. The inhibit voltage VINH is applied to the plurality of globalbit lines GB2(0)-GB2(x) by electrically connecting the plurality ofglobal bit lines GB2(0)-GB2(x) to a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHby turning on the plurality of NMOS transistors 130 k-13 xk in thekeeper circuit 130. The plurality of NMOS transistors 130 k-13 xk areturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 406 of the flow chart 400, byselecting the resistive change element O01 from the plurality ofresistive change elements E00-Oxy. The resistive change element O01 isselected from the plurality of resistive change elements E00-Oxy bycontrol logic, such as a processor, a controller, and a microcontroller.The resistive change elements E00-Ox0, E01, Ex1-Ox1 and E0 y-Oxy in theplurality of resistive change elements E00-Oxy that are not selected arereferred to as unselected resistive change elements.

The READ operation of the resistive change element O01 continues, assimilarly discussed above in step 408 of the flow chart 400, bypreparing the exemplary implementation of the first exemplaryarchitecture for determining a resistive state of the resistive changeelement O01. The exemplary implementation of the first exemplaryarchitecture is prepared for determining a resistive state of theresistive change element O01 by driving the voltage on the referenceline RL2 to the inhibit voltage VINH, changing electrical connections ofthe odd bit line Bo(0), changing electrical connections of the globalbit line GB2(0), and disconnecting a power supply, a voltage source, adriver circuit, or the device that supplies the inhibit voltage VINHfrom the global bit line GB2(0). The voltage on the reference line RL2is driven to the inhibit voltage VINH by electrically connecting thereference line RL2 through the second NMOS transistor 122 of thereference line connection circuit 120 and the second NMOS transistor 111p of the word line driver circuit 110 to a power supply, a voltagesource, a driver circuit, or other device that supplies the inhibitvoltage VINH. The second NMOS transistor 122 is turned on by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELo having a high level and, as discussed abovewith respect to providing neutral voltage conditions for the pluralityof resistive change elements E00-Oxy in the resistive change elementarray 100, the second NMOS transistor 111 p of the word line drivercircuit 110 is turned on.

The electrical connections of the odd bit line Bo(0) and the electricalconnections of the global bit line GB2(0) are changed and a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the global bitline GB2(0) so that a voltage indicative of the resistive state of theresistive change element O01 can be generated on the odd bit line Bo(0),the global bit line GB2(0), and the bus line BL2. The electricalconnections of the odd bit line Bo(0) are changed so that the odd bitline Bo(0) is in electrical communication with the global bit lineGB2(0). The odd bit line Bo(0) is electrically connected to the globalbit line GB2(0) by turning on the odd selection device No0. The oddselection device No0 is turned on by control logic, such as a processor,a controller, and a microcontroller, supplying a signal SSELo having ahigh level. The odd bit line Bo(0) may be electrically connected to theglobal bit line GB2(0) as part of driving the voltage on the referenceline RL2 to the inhibit voltage VINH as discussed above. It is notedthat the plurality of odd selection devices No0-Nox are turned on by thecontrol logic supplying a signal SSELo having a high level, and thus,the plurality of odd bit lines Bo(0)-Bo(x) are electrically connected tothe plurality of global bit lines GB2(0)-GB2(x).

The electrical connections of the global bit line GB2(0) are changed sothat the global bit line GB2(0) is in electrical communication with theodd bit line Bo(0) and the bus line BL2. The global bit line GB2(0) iselectrically connected to the odd bit line Bo(0) by turning on the oddselection device No0 as discussed above and the global bit line GB2(0)may be electrically connected to the odd bit line Bo(0) as part ofdriving the voltage on the reference line RL2 to the inhibit voltageVINH as discussed above. The global bit line GB2(0) is electricallyconnected to the bus line BL2 by turning on the PMOS transistor 140 g.The PMOS transistor 140 g is turned on by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signal YD0having a low level. A power supply, a voltage source, a driver circuit,or other device that supplies the inhibit voltage VINH is disconnectedfrom the global bit line GB2(0) by turning off the NMOS transistor 130k. The NMOS transistor 130 k is turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signal KEEPehaving a low level. It is noted that the control logic supplying asignal KEEPe having a low level also turns off NMOS transistors in theplurality of NMOS transistors 130 k-13 xk in electrical communicationwith global bit lines having even column numbers and disconnects globalbit lines having even column numbers from a power supply, a voltagesource, a driver circuit, or other device that supplies the inhibitvoltage VINH.

The READ operation of the resistive change element O01 continues, assimilarly discussed above in step 410 of the flow chart 400, bygenerating a voltage indicative of a resistive state of the resistivechange element O01. The voltage indicative of the resistive state of theresistive change element O01 is generated on the odd bit line Bo(0), theglobal bit line GB2(0), and the bus line BL2 by driving the voltage onthe word line W(1) to the system voltage VDD and sinking an amount ofcurrent for a READ operation from the bus line BL2. As discussed above,providing neutral voltage conditions for the plurality of resistivechange elements E00-Oxy causes voltages on the plurality of word linesW(0)-W(y), voltages on the plurality of even bit lines Be(0)-Be(x), andvoltages on the plurality of odd bit lines Bo(0)-Bo(x) to beapproximately equal to the inhibit voltage VINH. Also, as discussedabove, the plurality of global bit lines GB2(0)-GB2(x) are biased to theinhibit voltage VINH. Thus, for generating a voltage indicative of aresistive state of the resistive change element O01, a voltage on theword line W(1) transitions from the inhibit voltage VINH to the systemvoltage VDD and the voltages on the odd bit line Bo(0) and the globalbit line GB2(0) transition from the inhibit voltage VINH to a voltageindicative of a resistive state of the resistive change element O01.

The voltage transition of the voltage on the word line W(1) generallycorresponds with the voltage transition of the voltage on the topelectrode TE of the resistive change element O01 because the voltage onthe word line W(1) generally corresponds with the voltage on the topelectrode TE of the resistive change element O01. The voltage transitionof the voltage on the odd bit line Bo(0) generally corresponds with thevoltage transition of the voltage on the bottom electrode BE of theresistive change element O01 because the voltage on the odd bit lineBo(0) generally corresponds with the voltage on the bottom electrode BEof the resistive change element O01. The magnitude of the voltagetransition to place the top electrode TE of the resistive change elementO01 at the system voltage VDD for generating a voltage indicative of aresistive state of the resistive change element O01 is reduced becausethe voltage applied to the top electrode TE of the resistive changeelement O01 is not required to transition by the magnitude of the systemvoltage VDD. A voltage transition of the system voltage VDD minus theinhibit voltage VINH is required to place the top electrode at thesystem voltage VDD. For example, when the inhibit voltage VINH is VDD/2(half of the system voltage VDD) a voltage transition of VDD−VDD/2=VDD/2is required to place the top electrode at the system voltage VDD.Further, the number of voltage transitions for generating a voltageindicative of a resistive state of the resistive change element O01 isreduced because only voltages on the word line W(1), the global bit lineGB2(0), and the odd bit line Bo(0) are adjusted for generating a voltageindicative of a resistive state of the resistive change element O01. Itis noted that applying the inhibit voltage VINH to a top electrode, abottom electrode, or both a top electrode and a bottom electrode of aresistive change element limits a voltage applied across a resistivechange element to a voltage less than a voltage limit for disturbing aresistive state of a resistive change element while generating a voltageindicative of a resistive state of the resistive change element O01.

The voltage on the word line W(1) is driven from the inhibit voltageVINH to the system voltage VDD by changing the voltage supplied by theword line driver circuit 111 d from the inhibit voltage VINH to thesystem voltage VDD. The word line driver circuit 111 d changes fromsupplying the inhibit voltage VINH to the system voltage VDD based on asignal ITE1 supplied by control logic, such as a processor, acontroller, and a microcontroller. The write buffer circuit 150 does notsupply a voltage based on the write set signal WR0 and the write resetsignal WR1 supplied by control logic, such as a processor, a controller,and a microcontroller. The amount of current for a READ operation issunk from the bus line BL2 by the current source 160. The amount ofcurrent for a READ operation is based on the amount of current thatwould flow through a resistor having an intermediate resistance andhaving the system voltage VDD applied to one terminal of the resistorand the inhibit voltage VINH applied to the other terminal of theresistor. The amount of current that would flow through a resistorhaving an intermediate resistance and having the system voltage VDDapplied to one terminal of the resistor and the inhibit voltage VINHapplied to the other terminal of the resistor can be approximated by thefollowing equation, I=(VDD−VINH)/Intermediate Resistance. For example,when the intermediate resistance=5.5MΩ, the system voltage VDD=2V, andthe inhibit voltage VINH=1V, the current source 160 is configured tosink an amount of current that can be approximated asI=(2V−1V)/5.5MΩ=0.18 μA. It is noted that, ignoring leakage currents,the amount of current for the READ operation flows through the resistivechange element O01, the odd bit line Bo(0), the global bit line GB2(0),and the bus line BL2 to the current source 160.

The intermediate resistance sets a boundary for resistance values thatcorrespond with a low resistive state during READ operations andresistance values that correspond with a high resistive state duringREAD operations. The intermediate resistance is a design variable thatcan be selected by a circuit designer and the circuit designer typicallyselects an intermediate resistance greater than a model resistance for alow resistive state of a resistive change element and less than a modelresistance for a high resistive state of a resistive change element. Forexample, when a model resistance for a low resistive state of aresistive change element is 1M1Ω and a model resistance for a highresistive state of a resistive change elements is 10MΩ, a circuitdesigner can select an intermediate resistance of 5.5MΩ so thatresistive change elements having a resistance less than approximately5.5MΩ are determined to have a low resistive state during READoperations and resistive change elements having a resistance greaterthan approximately 5.5MΩ are determined to have a high resistive stateduring READ operations. It is noted that the intermediate resistance isnot limited to a resistance at the exact midpoint between a modelresistance for a low resistive state of a resistive change element and amodel resistance for a high resistive state of a resistive changeelement, but rather the intermediate resistance can be closer the modelresistance for the low resistive state or the model resistance for thehigh resistive state.

FIG. 1G-1 shows a current IO01 flowing through the resistive changeelement O01 from the top electrode TE to the bottom electrode BE becausethe top electrode TE is at the system voltage VDD and the bottomelectrode BE is at a voltage indicative of a resistive state of theresistive change element O01. While, ignoring leakage currents, theamount of the current flowing through the resistive change element O01,the odd bit line Bo(0), the global bit line GB2(0), and the bus line BL2are the same amount of current (the amount of current for the READoperation). Additionally, ignoring leakage currents, routing parasitics,and on resistance of the odd selection device No0, the voltage VBo(0) onthe odd bit line Bo(0), the voltage VGB2(0) on the global bit lineGB2(0), and the voltage on the bus line BL2 are generally the samevoltage and the voltage VBo(0) on the odd bit line Bo(0), the voltageVGB2(0) on the global bit line GB2(0), and the voltage on the bus lineBL2 are indicative of the resistive state of the resistive changeelement O01. It is noted that the voltage indicative of a resistivestate of the resistive change element O01 is discussed below withrespect to the voltage VGB2(0) on the global bit line GB2(0).

The voltage VGB2(0) on the global bit line GB2(0), ignoring leakagecurrents, routing parasitics, and on resistance of the odd selectiondevice No0, can be approximated by subtracting the voltage drop acrossthe resistive change element O01 from the voltage VW(1) on the word lineW(1). The voltage drop across the resistive change element O01 can beapproximated using Ohm's Law. Thus, the voltage VGB2(0) on the globalbit line GB2(0) can be approximated by the following equationVGB2(0)=VW(1)−(IO01×RO01), where VW(1) is the voltage on the word lineW(1), the current IO01 is the current flowing through resistive changeelement O01, and RO01 is the resistance of the resistive change elementO01. As shown by this equation, the voltage VGB2(0) on the global bitline GB2(0) changes when the resistance of the resistive change elementO01 changes because the voltage VW(1) on the word line W(1) and thecurrent IO01 flowing through the resistive change element O01 aregenerally the same for READ operations. For example, when VW(1)=2 volts,IO01=1/5.5 microamps, and RO01=5.5MΩ, the voltage VGB2(0)=2V−(1/5.5μA×5.5MΩ)=1V. For example, when VW(1)=2 volts, IO01=1/5.5 microamps, andRO01=1MΩ, the voltage VGB2(0)=2V−(1/5.5 μA×1MΩ)=1.82V. For example, whenVW(1)=2 volts, IO01=1/5.5 microamps, and RO01=10MΩ, the voltageVGB2(0)=2V−(1/5.5 μA×10 MΩ)=0.182V.

FIG. 1G-1 also shows leakage currents flowing through the resistivechange elements O00, O0 y in electrical communication with the odd bitline Bo(0) and leakage currents flowing through the resistive changeelements E01, Ex1-Ox1 in electrical communication with the word lineW(1). The leakage currents are shown using dashed lines in FIG. 1G-1.Leakage currents flow through the resistive change elements O00, O0 ybecause the bottom electrodes of the resistive change elements O00, O0 yare at a voltage indicative of a resistive state of the resistive changeelement O01 and the top electrodes of the resistive change elements O00,O0 y are the inhibit voltage VINH. Leakage currents flow throughresistive change elements E01, Ex1-Ox1 because the bottom electrodes ofthe resistive change elements E01, Ex1-Ox1 are at the inhibit voltageVINH and the top electrodes of the resistive change elements E01,Ex1-Ox1 are at the system voltage VDD. It is noted that leakage currentsmay flow through resistive change elements other than the resistivechange elements in electrical communication with the odd bit line Bo(0)and the resistive change elements in electrical communication with theword line W(1) because voltages on other lines may be impacted bygenerating a voltage indicative of a resistive state of the resistivechange element O01. It is also noted that leakage currents do notprevent the READ operation of the resistive change element O01 when theleakage currents are much less than the amount of the current IO01. Itis further noted that the voltage differences across the resistivechange elements that cause the leakage currents do not disturb theresistive states of the resistive change elements because the voltagedifferences are less than a voltage limit for disturbing a resistivestate of a resistive change element.

It is additionally noted that when the voltage VBo(0) on the odd bitline Bo(0) is less than the inhibit voltage VINH and the word linesW(0), W(y) in electrical communication with the other resistive changeelements O00, O0 y on the odd bit line Bo(0) are driven to the inhibitvoltage VINH, leakage currents flow into the odd bit line Bo(0) throughthe other resistive change elements O00, O0 y and pull up the voltageVBo(0) on the odd bit line Bo(0). It is also noted that when the voltageVBo(0) on the odd bit line Bo(0) is greater than the inhibit voltageVINH and the word lines W(0), W(y) in electrical communication with theother resistive change elements O00, O0 y on the odd bit line Bo(0) aredriven to the inhibit voltage VINH, leakage currents flow from the oddbit line Bo(0) through the other resistive change elements O00, O0 y andpull down the voltage VBo(0) on the bit line Bo(0). It is further notedthat when the voltage VBo(0) on the odd bit line Bo(0) is pulled up byleakage currents flowing into the odd bit line Bo(0) and when thevoltage VBo(0) on the odd bit line Bo(0) is pulled down by leakagecurrents flowing from the odd bit line Bo(0), the number of the wordlines W(0), W(y) should be small enough to allow a margin to determine aresistive state of the resistive change element O01.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 412 of the flow chart 400, bydetermining the resistive state of the resistive change element O01based on the voltage VGB2(0) on the global bit line GB2(0). Theresistive state of the resistive change element O01 is determined bycomparing the voltage VGB2(0) on with global bit line GB2(0) with theinhibit voltage VINH on the reference line RL2. As discussed above, thevoltage VGB2(0) on the global bit line GB2(0) is indicative of theresistive state of the resistive change element O01. For READ operationsthe inhibit voltage VINH is indicative of the intermediate resistancebecause the inhibit voltage VINH is equal to the system voltage VDDminus a voltage calculated by multiplying the amount of current for aREAD operation and the intermediate resistance of 5.5MΩ. For example,when the system voltage VDD=2V, the inhibit voltage VINH=1V, the amountof current for READ operations=1/5.5 μA, and the intermediateresistance=5.5MΩ, VINH=2V−(1/5.5 μA×5.5MΩ)=1V. When the voltage VGB2(0)on the global bit line GB2(0) is greater than the inhibit voltage (i.e.the voltage VGB2(0) on the global bit line GB2(0)>VINH) the resistanceof the resistive change element O01 is less than the intermediateresistance (i.e. RO01<intermediate resistance, where RO01 is theresistance of the resistive change element O01) and the resistive stateof the resistive change element O01 is determined to be a low resistivestate. When the voltage VGB2(0) on the global bit line GB2(0) is lessthan the inhibit voltage VINH (i.e. the voltage VGB2(0) on the globalbit line GB2(0)<VINH) the resistance of the resistive change element O01is greater than the intermediate resistance (i.e. RO01>intermediateresistance, where RO01 is the resistance of the resistive change elementO01) and the resistive state of resistive change element O01 isdetermined to be a high resistive state.

The first sense amplifier 200 receives the inhibit voltage VINH on thereference line RL2 and the voltage VGB2(0) on the global bit line GB2(0)and determines the resistive state of the resistive change element O01by comparing the inhibit voltage VINH on the reference line RL2 with thevoltage VGB2(0) on the global bit line GB2(0). The first sense amplifier200 outputs signals indicative of the resistive state of the resistivechange element O01 on two outputs. When the voltage VGB2(0) on theglobal bit line GB2(0) is greater than the inhibit voltage VINH, thefirst sense amplifier 200 outputs signals indicating the resistivechange element O01 has a low resistive state. When the voltage VGB2(0)on the global bit line GB2(0) is less than the inhibit voltage VINH, thefirst sense amplifier 200 outputs signals indicating the resistivechange element O01 has a high resistive state. The operation of thefirst sense amplifier 200 is discussed in greater detail with respect tothe simplified schematic diagram of the first sense amplifier 200 shownin FIG. 2A and the exemplary voltage waveforms for describing operationof the first sense amplifier 200 for READ operations of resistive changeelement O01. It is noted that providing the inhibit voltage VINH on thereference line RL2 to the first sense amplifier 200 can increase theaccuracy of determining the resistive state of the resistive changeelement O01 because the inhibit voltage VINH on the reference line RL2and the voltage VGB2(0) on the global bit line GB2(0) are subject tosimilar conditions.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 414 of the flow chart 400, byrestoring neutral voltage conditions for resistive change elementsimpacted by generating a voltage indicative of a resistive state of theresistive change element O01. Neutral voltage conditions are restoredfor resistive change elements impacted by generating a voltageindicative of a resistive state of the resistive change element O01 byfloating the plurality of odd bit lines Bo(0)-Bo(x) and applying theinhibit voltage VINH to the word line W(1). The plurality of even bitlines Be(0)-Be(x) are already floating because the plurality of evenselection devices Ne0-Nex are turned off. The inhibit voltage VINH isalready applied to the word lines W(0), W(y) because the word linedriver circuits 110 d, 11 yd are already supplying the inhibit voltageVINH. The plurality of odd bit lines Bo(0)-Bo(x) are floated bydisconnecting the plurality of odd bit lines Bo(0)-Bo(x) from theplurality of global bit lines GB2(0)-GB2(x) by turning off the pluralityof odd selection devices No0-Nox. The plurality of odd selection devicesNo0-Nox are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELo having a lowlevel. The inhibit voltage VINH is applied to the word line W(1) by theword line driver circuit 111 d driving the voltage on the word line W(1)to the inhibit voltage VINH. The word line driver circuit 111 d suppliesthe inhibit voltage VINH based on a signal ITE1 supplied by controllogic, such as a processor, a controller, and a microcontroller. Thus,the inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) with the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 416 of the flow chart 400, by biasingglobal bit lines impacted by generating a voltage indicative of aresistive state of the resistive change element O01. Global bit linesimpacted by generating a voltage indicative of a resistive state of theresistive change element O01 are biased to the inhibit voltage VINH byfloating the plurality of global bit lines GB2(0)-GB2(x) and applyingthe inhibit voltage VINH to global bit lines having even column numbers.The plurality of global bit lines GB2(0)-GB2(x) are floated bydisconnecting the plurality of global bit lines GB2(0)-GB2(x) from theplurality of odd bit lines Bo(0)-Bo(x) and disconnecting the global bitline GB2(0) from the bus line BL2. The plurality of global bit linesGB2(0)-GB2(x) are already disconnected from the plurality of even bitlines Be(0)-Be(x) because the plurality of even selection devicesNe0-Nex are turned off. The global bit lines other than global bit lineGB2(0) are already disconnected from the bus line BL2 because the PMOStransistors in the global bit line connection circuit 140 other thanPMOS transistor 140 g are turned off. The plurality of global bit linesGB2(0)-GB2(x) may be disconnected from the plurality of odd bit linesBo(0)-Bo(x) as part of restoring neutral voltage conditions forresistive change elements impacted by generating a voltage indicative ofa resistive state of the resistive change element O01 as discussedabove. The global bit line GB2(0) is disconnected from the bus line BL2by turning off the PMOS transistor 140 g. The PMOS transistor 140 g isturned off by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal YD0 having a high level. The inhibitvoltage VINH is already applied to the global bit lines having oddcolumn numbers because the global bit lines having odd column numbersare in electrical communication with a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHbecause the NMOS transistors 13 xk are turned on. The inhibit voltageVINH is applied to the global bit lines having even column numbers byelectrically connecting the global bit lines having even column numbersto a power supply, a voltage source, a driver circuit, or other devicethat supplies the inhibit voltage VINH by turning on the NMOStransistors 130 k. The NMOS transistors 130 k in electricalcommunication with the global bit lines having even column numbers areturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level.

Referring now to FIGS. 1H-1 and 1H-2, a simplified schematic diagram ofthe exemplary implementation of the first exemplary architecture showingcurrent flow through the resistive change element array 100 during aREAD operation of resistive change element O01 when resistive changeelement O01 has a high resistive state is illustrated. A READ operationof the resistive change element O01 when resistive change element O01has a high resistive state is performed in the same manner as a READoperation of the resistive change element O01 when resistive changeelement O01 has a low resistive as discussed above with respect to FIGS.1G-1 and 1G-2. However, a voltage indicative of a resistive state ofresistive change element O01 when resistive change element O01 has ahigh resistive state differs from a voltage indicative of a resistivestate of resistive change element O01 when resistive change element O01has a low resistive state. Thus, current flow through the resistivechange element array 100 during a READ operation of the resistive changeelement O01 when resistive change element O01 has a high resistive statemay differ from current flow through the resistive change element array100 during a READ operation of the resistive change element O01 whenresistive change element O01 has a low resistive state.

FIG. 1H-1 shows a current 1001 flowing through the resistive changeelement O01 from the top electrode TE to the bottom electrode BE becausethe top electrode TE is at the system voltage VDD and the bottomelectrode BE is at a voltage indicative of a resistive state of theresistive change element O01. FIG. 1H-1 also shows leakage currentsflowing through the resistive change elements O00, O0 y in electricalcommunication with the odd bit line Bo(0) and leakage currents flowingthrough the resistive change elements E01, Ex1-Ox1 in electricalcommunication with the word line W(1). The leakage currents are shownusing dashed lines in FIG. 1H-1. Leakage currents flow through theresistive change elements O00, O0 y because the bottom electrodes of theresistive change elements O00, O0 y are at a voltage indicative of aresistive state of the resistive change element O01 and the topelectrodes of the resistive change elements O00, O0 y are the inhibitvoltage VINH. Leakage currents flow through resistive change elementsE01, Ex1-Ox1 because the bottom electrodes of the resistive changeelements E01, Ex1-Ox1 are at the inhibit voltage VINH and the topelectrodes of the resistive change elements E01, Ex1-Ox1 are at thesystem voltage VDD. It is noted that leakage currents may flow throughresistive change elements other than the resistive change elements inelectrical communication with the odd bit line Bo(0) and the resistivechange elements in electrical communication with the word line W(1)because voltages on other lines may be impacted by generating a voltageindicative of a resistive state of the resistive change element O01. Itis also noted that leakage currents do not prevent the READ operation ofthe resistive change element 001 when the leakage currents are much lessthan the amount of the current IO01. It is further noted that thevoltage differences across the resistive change elements that cause theleakage currents do not disturb the resistive states of the resistivechange elements because the voltage differences are less than a voltagelimit for disturbing a resistive state of a resistive change element.

SET VERIFY operations of resistive change elements in the exemplaryimplementation of the first exemplary architecture can be performed in asimilar manner to READ operations of resistive change element O01discussed above, but with the current source 160 set to sink an amountof current for a SET VERIFY operation. The amount of current for a SETVERIFY operation is based on the amount of current that would flowthrough a resistor having a low resistance and having the system voltageVDD applied to one terminal of the resistor and the inhibit voltage VINHapplied to the other terminal of the resistor. The amount of currentthat would flow through a resistor having a low resistance and havingthe system voltage VDD applied to one terminal of the resistor and theinhibit voltage VINH applied to the other terminal of the resistor canbe approximated by the following equation, I=(VDD−VINH)/Low Resistance.For example, when the low resistance is 2MΩ, the system voltage VDD is2V, and the inhibit voltage VINH is 1V, the current source 160 isconfigured to sink an amount of current for a SET VERIFY operation thatcan be approximated as I=(2V−1V)/2MΩ=0.5 μA.

The low resistance sets an upper boundary for resistance values thatcorrespond with a low resistive state during SET VERIFY operations. Thelow resistance is a design variable that can be selected by a circuitdesigner and the circuit designer typically selects a low resistancegreater than a model resistance for a low resistive state of a resistivechange element so that resistive change elements can have resistancesgreater than the model resistance for the low resistive state and bedetermined to have a low resistive state during SET VERIFY operations.For example, when a model resistance for a low resistive state of aresistive change element is 1MΩ, a circuit designer can select a lowresistance of 2MΩ so that resistive change elements having a resistanceless than approximately 2MΩ are determined to have a low resistive stateduring SET VERIFY operations. It is noted that the circuit designertypically selects a low resistance greater than a model resistance for alow resistive state of a resistive change element and less than anintermediate resistance for READ operations.

RESET VERIFY operations of resistive change elements in the exemplaryimplementation of the first exemplary architecture can be performed in asimilar manner to READ operations of resistive change element O01discussed above, but with the current source 160 set to sink an amountof current for a RESET VERIFY operation. The amount of current for aRESET VERIFY operation is based on the amount of current that would flowthrough a resistor having a high resistance and having the systemvoltage VDD applied to one terminal of the resistor and the inhibitvoltage VINH applied to the other terminal of the resistor. The amountof current that would flow through a resistor having a high resistanceand having the system voltage VDD applied to one terminal of theresistor and the inhibit voltage VINH applied to the other terminal ofthe resistor can be approximated by the following equation,I=(VDD−VINH)/High Resistance. For example, when the high resistance is9MΩ, the system voltage VDD is 2V, and the inhibit voltage VINH is 1V,the current source 160 is configured to sink an amount of current for aRESET VERIFY operation that can be approximated as I=(2V−1V)/9MΩ=0.11μA.

The high resistance sets an upper boundary for resistance values thatcorrespond with a high resistive state during RESET VERIFY operations.The high resistance is a design variable that can be selected by acircuit designer and the circuit designer typically selects a highresistance less than a model resistance for a high resistive state of aresistive change element so that resistive change elements can haveresistances less than the model resistance for the high resistive stateand be determined to have a high resistive state during RESET VERIFYoperations. For example, when a model resistance for a high resistivestate of a resistive change element is 10MΩ, a circuit designer canselect a high resistance of 9MΩ so that resistive change elements havinga resistance greater than approximately 9MΩ are determined to have ahigh resistive state during RESET VERIFY operations. It is noted thatthe circuit designer typically selects a high resistance less than amodel resistance for a high resistive state of a resistive changeelement and greater than an intermediate resistance for READ operations.

Referring now to FIG. 2A, the first sense amplifier 200 receives thevoltage on the reference line RL2 labeled as the voltage REF, thevoltage on the bus line BL2, an initialization signal INIT, acomplementary initialization signal INITB, a first power on signal PONB,a second power on signal NON, a sense amplifier enable signal SAEN, anda bias current signal BIAS and outputs a voltage VoutB and a voltageVout. The voltage on the bus line BL2 is shown in FIG. 2A as the voltageVGB2(0) on the global bit line GB2(0) labeled as the voltage VGB fordescribing operation of the first sense amplifier 200 for READ operationof resistive change element O01. The first sense amplifier 200 includesa first input device 210, a second input device 220, a first load device230, a second load device 240, a current source 250, a power controldevice 260, and a latch device 270.

The first input device 210 includes a first PMOS transistor 212 having adrain terminal, a gate terminal, and a source terminal and a second PMOStransistor 214 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first PMOS transistor 212 is inelectrical communication with the drain terminal of the second PMOStransistor 214 and the first load device 230, the gate terminal of thefirst PMOS transistor 212 is in electrical communication with controllogic, such as a processor, a controller, and a microcontroller, toreceive the initialization signal INIT, and the source terminal of thefirst PMOS transistor 212 is in electrical communication with the busline BL2 to receive the voltage VGB. The drain terminal of the secondPMOS transistor 214 is in electrical communication with the drainterminal of the first PMOS transistor 212 and the first load device 230,the gate terminal of the second PMOS transistor 214 is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive the complementary initialization signalINITB, and the source terminal of the second PMOS transistor 214 is inelectrical communication with the reference line RL2 to receive thevoltage REF.

The second input device 220 includes a first PMOS transistor 222 havinga drain terminal, a gate terminal, and a source terminal and a secondPMOS transistor 224 having a drain terminal, a gate terminal, and asource terminal. The drain terminal of the first PMOS transistor 222 isin electrical communication with the drain terminal of the second PMOStransistor 224 and the second load device 240, the gate terminal of thefirst PMOS transistor 222 is in electrical communication with controllogic, such as a processor, a controller, and a microcontroller, toreceive the initialization signal INIT, and the source terminal of thefirst PMOS transistor 222 is in electrical communication with thereference line RL2 to receive the voltage REF and the source terminal ofthe second PMOS transistor 224. The drain terminal of the second PMOStransistor 224 is in electrical communication with the drain terminal ofthe first PMOS transistor 222 and the second load device 240, the gateterminal of the second PMOS transistor 224 is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive the complementary initialization signalINITB, and the source terminal of the second PMOS transistor 224 is inelectrical communication with the reference line RL2 to receive thevoltage REF and the source terminal of the first PMOS transistor 222.

The first load device 230 includes a first NMOS transistor 231 having adrain terminal, a gate terminal, and a source terminal, a first PMOStransistor 232 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 233 having a drain terminal, a gateterminal, and a source terminal, a second PMOS transistor 234 having adrain terminal, a gate terminal, and a source terminal, a firstcapacitor connected PMOS transistor 235 having a drain terminal, a gateterminal, and a source terminal, and a second capacitor connected PMOStransistor 236 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 231 is inelectrical communication with the power control device 260, the secondload device 240, the drain terminal of the first PMOS transistor 232,the drain terminal of the second PMOS transistor 234, and the sourceterminal of the second NMOS transistor 233. The gate terminal of thefirst NMOS transistor 231 is in electrical communication with the firstinput device 210. The source terminal of the first NMOS transistor 231is in electrical communication with the current source 250 and thesecond load device 240. The drain terminal of the first PMOS transistor232 is in electrical communication with the drain terminal of the secondPMOS transistor 234, the source terminal of the second NMOS transistor233, the second load device 240, the power control device 260, and thedrain terminal of the first NMOS transistor 231. The gate terminal ofthe first PMOS transistor 232 is in electrical communication with thesource terminal of the second PMOS transistor 234, the drain terminal ofthe second NMOS transistor 233, the gate terminal of the first capacitorconnected PMOS transistor 235, and the gate terminal of the secondcapacitor connected PMOS transistor 236. The source terminal of thefirst PMOS transistor 232 is in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The drain terminal of the second NMOStransistor 233 is in electrical communication with the source terminalof the second PMOS transistor 234, the gate terminal of the first PMOStransistor 232, the gate terminal of the first capacitor connected PMOStransistor 235, and the gate terminal of the second capacitor connectedPMOS transistor 236. The gate terminal of the second NMOS transistor 233is in electrical communication with control logic, such as a processor,a controller, and a microcontroller, to receive the initializationsignal INIT. The source terminal of the second NMOS transistor 233 is inelectrical communication with the drain terminal of the second PMOStransistor 234, the drain terminal of the first PMOS transistor 232, thesecond load device 240, the power control device 260, and the drainterminal of the first NMOS transistor 231. The drain terminal of thesecond PMOS transistor 234 is in electrical communication with thesource terminal of the second NMOS transistor 233, the drain terminal ofthe first PMOS transistor 232, the second load device 240, the powercontrol device 260, and the drain terminal of the first NMOS transistor231. The gate terminal of the second PMOS transistor 234 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the complementaryinitialization signal INITB. The source terminal of the second PMOStransistor 234 is in electrical communication with the gate terminal ofthe first PMOS transistor 232, the drain terminal of the second NMOStransistor 233, the gate terminal of the first capacitor connected PMOStransistor 235, and the gate terminal of the second capacitor connectedPMOS transistor 236. The drain terminal and the source terminal of thefirst capacitor connected PMOS transistor 235 are in electricalcommunication and the drain terminal and the source terminal are inelectrical communication with the second load device 240. The gateterminal of the first capacitor connected PMOS transistor 235 is inelectrical communication with the drain terminal of the second NMOStransistor 233, the source terminal of the second PMOS transistor 234,the gate terminal of the first PMOS transistor 232, and the gateterminal of the second capacitor connected PMOS transistor 236. Thedrain terminal and the source terminal of the second capacitor connectedPMOS transistor 236 are in electrical communication and the drainterminal and the source terminal are in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The gate terminal of the secondcapacitor connected PMOS transistor 236 is in electrical communicationwith the gate terminal of the first PMOS transistor 232, the sourceterminal of the second PMOS transistor 234, the drain terminal of thesecond NMOS transistor 233, and the gate terminal of the first capacitorconnected PMOS transistor 235.

The second load device 240 includes a first NMOS transistor 241 having adrain terminal, a gate terminal, and a source terminal, a first PMOStransistor 242 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 243 having a drain terminal, a gateterminal, and a source terminal, a second PMOS transistor 244 having adrain terminal, a gate terminal, and a source terminal, a firstcapacitor connected PMOS transistor 245 having a drain terminal, a gateterminal, and a source terminal, and a second capacitor connected PMOStransistor 246 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 241 is inelectrical communication with the power control device 260, the firstload device 230, the drain terminal of the first PMOS transistor 242,the drain terminal of the second PMOS transistor 244, and the sourceterminal of the second NMOS transistor 243. The gate terminal of thefirst NMOS transistor 241 is in electrical communication with the secondinput device 220. The source terminal of the first NMOS transistor 241is in electrical communication with the current source 250 and the firstload device 230. The drain terminal of the first PMOS transistor 242 isin electrical communication with the drain terminal of the second PMOStransistor 244, the source terminal of the second NMOS transistor 243,the first load device 230, the power control device 260, and the drainterminal of the first NMOS transistor 241. The gate terminal of thefirst PMOS transistor 242 is in electrical communication with the sourceterminal of the second PMOS transistor 244, the drain terminal of thesecond NMOS transistor 243, the gate terminal of the first capacitorconnected PMOS transistor 245, and the gate terminal of the secondcapacitor connected PMOS transistor 246. The source terminal of thefirst PMOS transistor 242 is in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The drain terminal of the second NMOStransistor 243 is in electrical communication with the source terminalof the second PMOS transistor 244, the gate terminal of the first PMOStransistor 242, the gate terminal of the first capacitor connected PMOStransistor 245, and the gate terminal of the second capacitor connectedPMOS transistor 246. The gate terminal of the second NMOS transistor 243is in electrical communication with control logic, such as a processor,a controller, and a microcontroller, to receive the initializationsignal INIT. The source terminal of the second NMOS transistor 243 is inelectrical communication with the drain terminal of the second PMOStransistor 244, the drain terminal of the first PMOS transistor 242, thefirst load device 230, the power control device 260, and the drainterminal of the first NMOS transistor 241. The drain terminal of thesecond PMOS transistor 244 is in electrical communication with thesource terminal of the second NMOS transistor 243, the drain terminal ofthe first PMOS transistor 242, the first load device 230, the powercontrol device 260, and the drain terminal of the first NMOS transistor241. The gate terminal of the second PMOS transistor 244 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the complementaryinitialization signal INITB. The source terminal of the second PMOStransistor 244 is in electrical communication with the gate terminal ofthe first PMOS transistor 242, the drain terminal of the second NMOStransistor 243, the gate terminal of the first capacitor connected PMOStransistor 245, and the gate terminal of the second capacitor connectedPMOS transistor 246. The drain terminal and the source terminal of thefirst capacitor connected PMOS transistor 245 are in electricalcommunication and the drain terminal and the source terminal are inelectrical communication with the first load device 230. The gateterminal of the first capacitor connected PMOS transistor 245 is inelectrical communication with the drain terminal of the second NMOStransistor 243, the source terminal of the second PMOS transistor 244,the gate terminal of the first PMOS transistor 242, and the gateterminal of the second capacitor connected PMOS transistor 246. Thedrain terminal and the source terminal of the second capacitor connectedPMOS transistor 246 are in electrical communication and the drainterminal and the source terminal are in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The gate terminal of the secondcapacitor connected PMOS transistor 246 is in electrical communicationwith the gate terminal of the first PMOS transistor 242, the sourceterminal of the second PMOS transistor 244, the drain terminal of thesecond NMOS transistor 243, and the gate terminal of the first capacitorconnected PMOS transistor 245.

The current source 250 includes a first NMOS transistor 252 have a drainterminal, a gate terminal, and a source terminal and a second NMOStransistor 254 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 252 is inelectrical communication with the first load device 230 and the secondload device 240. The gate terminal of the first NMOS transistor 252 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the sense amplifier enablesignal SAEN. The source terminal of the first NMOS transistor 252 is inelectrical communication with the drain terminal of the second NMOStransistor 254. The drain terminal of the second NMOS transistor 254 isin electrical communication with the source terminal of the first NMOStransistor 252. The gate terminal of the second NMOS transistor 254 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the bias current signalBIAS. The source terminal of the second NMOS transistor 254 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground.

The power control device 260 includes a PMOS transistor 262 having adrain terminal, a gate terminal, and a source terminal, a first NMOStransistor 264 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 266 having a drain terminal, a gateterminal, and a source terminal, and a third NMOS transistor 268 havinga drain terminal, a gate terminal, and a source terminal. The drainterminal of the PMOS transistor 262 is in electrical communication withthe latch device 270. The gate terminal of the PMOS transistor 262 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the first power on signalPONB. The source terminal of the PMOS transistor 262 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the system voltage VDD. The drain terminalof the first NMOS transistor 264 is in electrical communication with thelatch device 270. The gate terminal of the first NMOS transistor 264 isin electrical communication control logic, such as a processor, acontroller, and a microcontroller, to receive the second power on signalNON. The source terminal of the first NMOS transistor 264 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The drainterminal of the second NMOS transistor 266 is in electricalcommunication with the latch device 270. The gate terminal of the secondNMOS transistor 266 is in electrical communication with control logic,such as a processor, a controller, and a microcontroller, to receive thefirst power on signal PONB. The source terminal of the second NMOStransistor 266 is in electrical communication with the first load device230. The drain terminal of the third NMOS transistor 268 is inelectrical communication with the second load device 240. The gateterminal of the third NMOS transistor 268 is in electrical communicationwith control logic, such as a processor, a controller, and amicrocontroller, to receive the first power on signal PONB. The sourceterminal of the third NMOS transistor 268 is in electrical communicationwith the latch device 270. Alternatively, each of the second NMOStransistor 266 and the third NMOS transistor 268 may be replaced with aNMOS transistor and a PMOS transistor in electrical communication inparallel, with each of the NMOS transistors having a drain terminal, agate terminal, and a source terminal, each of the PMOS transistorshaving a drain terminal, a gate terminal, and a source terminal, thegate terminals of both NMOS transistors in electrical communication witha circuit to receive a signal to turn on and turn off both NMOStransistors, the gate terminals of both PMOS transistors in electricalcommunication with a circuit to receive a signal to turn on and turn offboth PMOS transistors, and the signals being coordinated such that bothNMOS transistors and both PMOS transistors are turned on and turned offat generally the same time.

The latch device 270 includes a first PMOS transistor 272 having a drainterminal, a gate terminal, and a source terminal, a first NMOStransistor 274 having a drain terminal, a gate terminal, and a sourceterminal, a second PMOS transistor 276 having a drain terminal, a gateterminal, and a source terminal, and a second NMOS transistor 278 havinga drain terminal, a gate terminal, and a source terminal. The drainterminal of the first PMOS transistor 272 is in electrical communicationwith the gate terminal of the second PMOS transistor 276, the gateterminal of the second NMOS transistor 278, the power control device260, and the drain terminal of the first NMOS transistor 274. The gateterminal of the first PMOS transistor 272 is in electrical communicationwith the drain terminal of the second PMOS transistor 276, the drainterminal of the second NMOS transistor 278, the power control device260, and the gate terminal of the first NMOS transistor 274. The sourceterminal of the first PMOS transistor 272 is in electrical communicationwith the power control device 260 and the source terminal of the secondPMOS transistor 276. The drain terminal of the first NMOS transistor 274is in electrical communication with the power control device 260, thegate terminal of the second PMOS transistor 276, the gate terminal ofthe second NMOS transistor 278, and the drain terminal of the first PMOStransistor 272. The gate terminal of the first NMOS transistor 274 is inelectrical communication with the drain terminal of the second PMOStransistor 276, the drain terminal of the second NMOS transistor 278,the power control device 260, and the gate terminal of the first PMOStransistor 272. The source terminal of the first NMOS transistor 274 isin electrical communication with the power control device 260 and thesource terminal of the second NMOS transistor 278. The drain terminal ofthe second PMOS transistor 276 is in electrical communication with thepower control device 260, the gate terminal of the first PMOS transistor272, the gate terminal of the first NMOS transistor 274, and the drainterminal of the second NMOS transistor 278. The gate terminal of thesecond PMOS transistor 276 is in electrical communication with the drainterminal of the first PMOS transistor 272, the drain terminal of thefirst NMOS transistor 274, the power control device 260, and the gateterminal of the second NMOS transistor 278. The source terminal of thesecond PMOS transistor 276 is in electrical communication with the powercontrol device 260 and the source terminal of the first PMOS transistor272. The drain terminal of the second NMOS transistor 278 is inelectrical communication with the power control device 260, the gateterminal of the first PMOS transistor 272, the gate terminal of thefirst NMOS transistor 274, and the drain terminal of the second PMOStransistor 276. The gate terminal of the second NMOS transistor 278 isin electrical communication with the drain terminal of the first PMOStransistor 272, the drain terminal of the first NMOS transistor 274, thepower control device 260, and the gate terminal of the second PMOStransistor 276. The source terminal of the second NMOS transistor 278 isin electrical communication with the power control device 260 and thesource terminal of the first NMOS transistor 274.

Referring now to the simplified schematic diagram of the first senseamplifier 200 shown in FIG. 2A, the first input device 210 receives thevoltage on the reference line RL2 labeled as the voltage REF, thevoltage VGB2(0) on the global bit line GB2(0) labeled as the voltageVGB, the initialization signal INIT, and the complementaryinitialization signal INITB. The second input device 220 receives thevoltage on the reference line RL2 labeled as the voltage REF, theinitialization signal INIT, and the complementary initialization signalINITB. The first load device 230 receives the initialization signal INITand the complementary initialization signal INITB and the second loaddevice 240 receives the initialization signal INIT and the complementaryinitialization signal INITB. The current source 250 receives the senseamplifier enable signal SAEN and the bias current signal BIAS. The powercontrol device 260 receives the first power on signal PONB and thesecond power on signal NON. Control logic, such as a processor, acontroller, and a microcontroller, supplies the initialization signalINIT, the complementary initialization signal INITB, the sense amplifierenable signal SAEN, the bias current signal BIAS, the first power onsignal PONB, and the second power on signal NON to the first senseamplifier 200. Exemplary voltage waveforms for the initialization signalINIT, the complementary initialization signal INITB, the sense amplifierenable signal SAEN, the first power on signal PONB, and the second poweron signal NON for describing operation of the first sense amplifier 200for READ operations of resistive change element O01 are shown in FIG.2B. Additionally, although an exemplary voltage waveform for the biascurrent signal BIAS is not shown in FIG. 2B, the control logic suppliesthe bias current signal BIAS. The control logic supplies the senseamplifier enable signal SAEN to enable and disable the current source250 and the bias current signal BIAS to set the amount of current sunkby the current source 250. Also, exemplary voltage waveforms for thesignal YD0, the signal SSELo, the signal KEEPe, the voltage VW(1) on theword line W(1), the voltage on the reference line RL2 labeled as thevoltage REF, and the voltage VGB2(0) on the global bit line GB2(0)labeled as the voltage VGB for describing operation of the first senseamplifier 200 for READ operations of resistive change element O01 areshown in FIG. 2B. Further, FIG. 2B shows two exemplary voltage waveformsfor the voltage VGB, a voltage waveform for when the resistive changeelement O01 has a low resistive state and a voltage waveform for whenthe resistive change element O01 has a high resistive state.

The first sense amplifier 200 is in an initializing configuration whenthe initialization signal INIT has a high level and the complementaryinitialization signal INITB has a low level and the first senseamplifier 200 is in a comparing configuration when the initializationsignal INIT has a low level and the complementary initialization signalINITB has a high level. When the first sense amplifier 200 is in aninitializing configuration the first PMOS transistor 232 of the firstload device 230 is electrically connected to function as a diode and thefirst PMOS transistor 242 of the second load device 240 is electricallyconnected to function as a diode. When the first sense amplifier 200 isin a comparing configuration the first PMOS transistor 232 iselectrically connected to function as a resistor and the first PMOStransistor 242 is electrically connected to function as a resistor withthe operating points of the first PMOS transistor 232 and the secondPMOS transistor 242 set to compensate for performance differencesbetween the first load device 230 and the second load device 240 bykeeping the gate voltage of the first PMOS transistor 232 at a biasvoltage VB232 and the gate voltage of the first PMOS transistor 242 at abias voltage VB242. Additionally, when the initialization signal INIThas a high level and the complementary initialization signal INITB has alow level the first input device 210 provides the voltage on thereference line RL2 to the first load device 230 and the second inputdevice 220 provides the voltage on the reference line RL2 to the secondload device 240. Further, when the initialization signal INIT has a lowlevel and the complementary initialization signal INITB has a high levelthe first input device 210 provides the voltage VGB2(0) on the globalbit line GB2(0) to the first load device 230 and the second input device220 provides the voltage on the reference line RL2 to the second loaddevice 240.

The first sense amplifier 200 is initialized to generate the biasvoltage VB232 for setting the operating point of the first PMOStransistor 232 and the bias voltage VB242 for setting the operatingpoint of the first PMOS transistor 242 before comparing the voltageVGB2(0) on the global bit line GB2(0) with the voltage on the referenceline RL2. As shown in FIG. 2B, at the start of initializing the firstsense amplifier 200, the first sense amplifier 200 is in theinitializing configuration, the initialization signal INIT has a highlevel, the complementary initialization signal INITB has a low level,the sense amplifier enable signal SAEN transitions to a high level, thefirst power on signal PONB transitions to a high level, and the secondpower on signal NON transitions to a low level. During initializing thefirst sense amplifier 200, the bias voltage VB232 for setting theoperating point for the first PMOS transistor 232 of the first loaddevice 230 is generated and the bias voltage VB242 for setting theoperating point for the first PMOS transistor 242 of the second loaddevice 240 is generated.

The bias voltage VB232 is generated on the first line L237 and thesecond line L238 of the first load device 230 and the bias voltage VB242is generated on the first line L247 and the second line L248 of thesecond load device 240. The voltage on the first line L237 and thevoltage on the second line L238 of the first load device 230 aregenerally the same voltage because turning on the second NMOS transistor233 and the second PMOS transistor 234 electrically connects the firstPMOS transistor 232 to function as a diode by electrically connectingthe first line L237 and the second line L238. The voltage on the firstline L247 and the voltage on the second line L248 of the second loaddevice 240 are generally the same voltage because turning on the secondNMOS transistor 243 and the second PMOS transistor 244 electricallyconnects the first PMOS transistor 242 to function as a diode byelectrically connecting the first line L247 and the second line L248.The bias voltage VB232 is based on an amount of current flowing throughthe first load device 230 and the bias voltage VB242 is based on anamount of current flowing through the second load device 240. The sum ofthe amount of current flowing through the first load device 230 and theamount of current flowing through the second load device 240 is equal toan amount of current sunk by the current source 250.

A current path through the first load device 230 is created byelectrically connecting the first PMOS transistor 232 to function as adiode and providing the inhibit voltage VINH on the reference line RL2to the gate terminal of the first NMOS transistor 231. The first PMOStransistor 232 is electrically connected to function as a diode byturning on the second NMOS transistor 233 and the second PMOS transistor234. The voltage on the reference line RL2 is driven to the inhibitvoltage VINH by turning on the second NMOS transistor 122 in thereference line connection circuit 120 and the second NMOS transistor 122may be turned on as part of preparing the exemplary implementation ofthe first exemplary architecture for determining a resistive state ofthe resistive change element O01 as discussed above. The inhibit voltageVINH is provided to the gate terminal of the first NMOS transistor 231of the first load device 230 by turning off the first PMOS transistor212 of the first input device 210 and turning on the second PMOStransistor 214 of the first input device 210. The second NMOS transistor233 of the first load device 230 is turned on and the first PMOStransistor 212 of the first input device 210 is turned off because theinitialization signal INIT has a high level. The second PMOS transistor234 of the first load device 230 and the second PMOS transistor 214 ofthe first input device 210 are turned on because the complementaryinitialization signal INITB has a low level.

A current path through the second load device 240 is created byelectrically connecting the first PMOS transistor 242 to function as adiode and providing the inhibit voltage VINH on the reference line RL2to the gate terminal of the first NMOS transistor 241. The first PMOStransistor 242 is electrically connected to function as a diode byturning on the second NMOS transistor 243 and the second PMOS transistor244. The voltage on the reference line RL2 is driven to the inhibitvoltage VINH by turning on the second NMOS transistor 122 in thereference line connection circuit 120 and the second NMOS transistor 122may be turned on as part of preparing the exemplary implementation ofthe first exemplary architecture for determining a resistive state ofthe resistive change element O01 as discussed above. The inhibit voltageVINH is provided to the gate terminal of the first NMOS transistor 241of the second load device 240 by turning off the first PMOS transistor222 of the second input device 220 and turning on the second PMOStransistor 224 of the second input device 220. The second NMOStransistor 243 of the second load device 240 is turned on and the firstPMOS transistor 222 of the second input device 220 is turned off becausethe initialization signal INIT has a high level. The second PMOStransistor 244 of the second load device 240 and the second PMOStransistor 224 of the second input device 220 are turned on because thecomplementary initialization signal INITB has a low level.

The first capacitor connected PMOS transistor 235 and the secondcapacitor connected PMOS transistor 236 of the first load device 230 arecharged to the bias voltage VB232 because the first capacitor connectedPMOS transistor 235 and the second capacitor connected PMOS transistor236 are electrically connected to the second line L238. The bias voltageVB232 on the first line L237 and the second line L238 is approximatelyequal to the voltage on the drain terminal of the first PMOS transistor232. The first capacitor connected PMOS transistor 245 and the secondcapacitor connected PMOS transistor 246 of the second load device 240are charged to the bias voltage VB242 because the first capacitorconnected PMOS transistor 245 and the second capacitor connected PMOStransistor 246 are electrically connected to the second line L248. Thebias voltage VB242 on the first line L247 and the second line L248 isapproximately equal to the voltage on the drain terminal of the firstPMOS transistor 242.

The impact of noise and voltage offsets on the bias voltage VB232 andthe bias voltage VB242 are reduced because the first capacitor connectedPMOS transistor 235 of the first load device 230 and the first capacitorconnected PMOS transistor 245 of the second load device 240 are crosscoupled so that noise and voltage offsets on line L237 and line L238 ofthe first load device 230 are similar to noise and voltage offsets online L247 and line L248 of the second load device 240. The impact ofvoltage transients on the bias voltage VB232 and the bias voltage VB242are reduced by the voltage levels of the initialization signal INIT andthe complementary initialization signal INITB being offset. Voltagetransients introduced through gate to channel capacitance of the secondNMOS transistor 233 by turning on and off the second NMOS transistor 233and voltage transients introduced through gate to channel capacitance ofthe second PMOS transistor 234 by turning on and off the second PMOStransistor 234 are offset because the voltage levels of theinitialization signal INIT and the complementary initialization signalINITB are offset. Thus, voltage transients introduced through gate tochannel capacitance of the second NMOS transistor 233 by turning on andoff the second NMOS transistor 233 and voltage transients introducedthrough gate to channel capacitance of the second PMOS transistor 234 byturning on and off the second PMOS transistor 234 at least partiallycancel each other because the voltage transients are offset. Voltagetransients introduced through gate to channel capacitance of the secondNMOS transistor 243 by turning on and off the second NMOS transistor 243and voltage transients introduced through gate to channel capacitance ofthe second PMOS transistor 244 by turning on and off the second PMOStransistor 244 are offset because the voltage levels of theinitialization signal INIT and the complementary initialization signalINITB are offset. Thus, voltage transients introduced through gate tochannel capacitance of the second NMOS transistor 243 by turning on andoff the second NMOS transistor 243 and voltage transients introducedthrough gate to channel capacitance of the second PMOS transistor 244 byturning on and off the second PMOS transistor 244 at least partiallycancel each other because the voltage transients are offset.

After initializing the first sense amplifier 200 to generate the biasvoltage VB232 and the bias voltage VB242, the first sense amplifier 200compares the voltage VGB2(0) on the global bit line GB2(0) with thevoltage on the reference line RL2. The first PMOS transistor 232 iselectrically connected to function as a resistor with the gate voltageof the first PMOS transistor 232 kept at the bias voltage VB232 and thefirst PMOS transistor 242 is electrically connected to function as aresistor with the gate voltage of the first PMOS transistor 242 kept atthe bias voltage VB242. Keeping the gate voltage of the first PMOStransistor 232 at the bias voltage VB232 and the gate voltage of thefirst PMOS transistor 242 at the bias voltage VB242 increases theaccuracy of comparing the voltage VGB2(0) on the global bit line GB2(0)with the voltage on the reference line RL2 because keeping the gatevoltage of the first PMOS transistor 232 at the bias voltage VB232 andthe gate voltage of the first PMOS transistor 242 at the bias voltageVB242 compensates for performance differences between the first loaddevice 230 and the second load device 240.

As shown in FIG. 2B, at the start of comparing the voltage VGB2(0) onthe global bit line GB2(0) with the voltage on the reference line RL2,the initialization signal INIT transitions to a low level, thecomplementary initialization signal INITB transitions to a high level,the sense amplifier enable signal SAEN has a high level, the first poweron signal PONB has a high level, and the second power on signal NON hasa low level. As discussed above, when the initialization signal INIT hasa low level and the complementary initialization signal INITB has a highlevel, the first sense amplifier 200 is in a comparing configuration,the first input device 210 provides the voltage VGB2(0) on the globalbit line GB2(0) to the first load device 230, and the second inputdevice 220 provides the voltage on the reference line RL2 to the secondload device 240. During comparing the voltage VGB2(0) on the global bitline GB2(0) with the voltage on the reference line RL2, a voltage VS237is generated on the first line L237 of the first load device 230 and avoltage VS247 is generated on the first line L247 of the second loaddevice 240 with the voltage VS237 and the voltage VS247 being indicativeof a difference between the voltage VGB2(0) on the global bit lineGB2(0) and the voltage on the reference line RL2. The voltage VS237 isbased on an amount of current flowing through the first load device 230and the voltage VS247 is based on an amount of current flowing throughthe second load device 240. The sum of the amount of current flowingthrough the first load device 230 and the amount of current flowingthrough the second load device 240 is equal to an amount of current sunkby the current source 250.

A current path through the first load device 230 is created by keepingthe gate voltage of first PMOS transistor 232 at the bias voltage VB232and providing the voltage VGB2(0) on the global bit line GB2(0) to thegate terminal of the first NMOS transistor 231. The gate voltage of thefirst PMOS transistor 232 is kept at the bias voltage VB232 bydisconnecting the first line L237 from the second line L238 with thefirst capacitor connected PMOS transistor 235 and the second capacitorconnected PMOS transistor 236 charged to the bias voltage VB232. Afterdisconnecting the first line L237 from the second line L238 the voltageon the second line L238 and the gate voltage of the first PMOStransistor 232 are kept at the bias voltage VB232 by the first capacitorconnected PMOS transistor 235 and the second capacitor connected PMOStransistor 236. The first line L237 is disconnected from the second lineL238 by turning off the second NMOS transistor 233 and the second PMOStransistor 234. The voltage VGB2(0) on the global bit line GB2(0) isprovided to the gate terminal of the first NMOS transistor 231 of thefirst load device 230 by turning on the first PMOS transistor 212 of thefirst input device 210 and turning off the second PMOS transistor 214 ofthe first input device 210. The voltage VGB2(0) on the global bit lineGB2(0) is driven to a voltage indicative of a resistive state of theresistive change element O01 as discussed above with respect togenerating a voltage indicative of a resistive state of the resistivechange element O01. The second NMOS transistor 233 of the first loaddevice 230 is turned off and the first PMOS transistor 212 of the firstinput device 210 is turned on because the initialization signal INIT hasa low level. The second PMOS transistor 234 of the first load device 230and the second PMOS transistor 214 of the first input device 210 areturned off because the complementary initialization signal INITB has ahigh level.

A current path through the second load device 240 is created by keepingthe gate voltage of first PMOS transistor 242 at the bias voltage VB242and providing the voltage on the reference line RL2 to the gate terminalof the first NMOS transistor 241. The gate voltage of the first PMOStransistor 242 is kept at the bias voltage VB242 by disconnecting thefirst line L247 from the second line L248 with the first capacitorconnected PMOS transistor 245 and the second capacitor connected PMOStransistor 246 charged to the bias voltage VB242. After disconnectingthe first line L247 from the second line L248 the voltage on the secondline L248 and the gate voltage of the first PMOS transistor 242 are keptat the bias voltage VB242 by the first capacitor connected PMOStransistor 245 and the second capacitor connected PMOS transistor 246.The first line L247 is disconnected from the second line L248 by turningoff the second NMOS transistor 243 and the second PMOS transistor 244.The voltage on the reference line RL2 is provided to the gate terminalof the first NMOS transistor 241 of the second load device 240 byturning on the first PMOS transistor 222 of the second input device 220and turning off the second PMOS transistor 224 of the second inputdevice 220. The voltage on the reference line RL2 is driven to theinhibit voltage VINH by turning on the second NMOS transistor 122 in thereference line connection circuit 120 and the second NMOS transistor 122may be turned on as part of preparing the exemplary implementation ofthe first exemplary architecture for determining a resistive state ofthe resistive change element O01 as discussed above. The second NMOStransistor 243 of the second load device 240 is turned off and the firstPMOS transistor 222 of the second input device 210 is turned on becausethe initialization signal INIT has a low level. The second PMOStransistor 244 of the second load device 240 and the second PMOStransistor 224 of the second input device 220 are turned off because thecomplementary initialization signal INITB has a high level.

The amount of current flowing through the first load device 230 and theamount of current flowing through the second load device 240 generallychange when the voltage VGB2(0) on the global bit line GB2(0) changesbecause the voltage on the reference line RL2 is the inhibit voltageVINH and the inhibit voltage VINH is generally the same for READoperations. When the voltage VGB2(0) on the global bit line GB2(0)increases, the amount of current flowing through the first load device230 increases, the amount of current flowing through the second loaddevice 240 decreases, the voltage VS237 on the first line L237 of thefirst load device 230 decreases, and the voltage VS247 on the first lineL247 of the second load device 240 increases. When the voltage VGB2(0)on the global bit line GB2(0) decreases, the amount of current flowingthrough first load device 230 decreases, the amount of current flowingthrough the second load device 240 increases, the voltage VS237 on thefirst line L237 of the first load device 230 increases, and the voltageVS247 on the first line L247 of the second load device 240 decreases.

The difference between the voltage VS237 on the first line L237 in thefirst load device 230 and the voltage VS247 on the first line L247 inthe second load device 240 is indicative of a resistive state of theresistive change element O01. When the resistive change element O01 hasa low resistive state, the voltage VGB2(0) on the global bit line GB2(0)is greater than the inhibit voltage VINH, the amount of current flowingthrough the first load device 230 is greater than the amount of currentflowing through the second load device 240 and the voltage VS237 onfirst line L237 of the first load device 230 is less than the voltageVS247 on the first line L247 of the second load device 240. When theresistive change element O01 has a high resistive state, the voltageVGB2(0) on the global bit line GB2(0) is less than the inhibit voltageVINH, the amount of current flowing through the first load device 230 isless than the amount of current flowing through the second load device240 and the voltage VS237 on first line L237 of the first load device230 is greater than the voltage VS247 on the first line L247 of thesecond load device 240.

While the first power on signal PONB has a high level, the power controldevice 260 provides the voltage VS237 to the first output 201, the gateterminal of the second PMOS transistor 276 of the latch device 270, andthe gate terminal of the second NMOS transistor 278 of the latch device270 because the second NMOS transistor 266 of the power control device260 is turned on. Also, while the first power on signal PONB has a highlevel, the power control device 260 provides the voltage VS247 to thesecond output 202, the gate terminal of the first PMOS transistor 272 ofthe latch device 270, and the gate terminal of the first NMOS transistor274 of the latch device 270 because the third NMOS transistor 268 of thepower control device 260 is turned on. When resistive change element O01has a low resistive state, the voltage VS237 has a voltage level lessthan a voltage level of the voltage VS247, the gate voltage of the firstPMOS transistor 272 is greater than the gate voltage of the second PMOStransistor 276 and the first PMOS transistor 272 is turned on less thanthe second PMOS transistor 276. Additionally, when resistive changeelement O01 has a low resistive state, the gate voltage of the firstNMOS transistor 274 is greater than the gate voltage of the second NMOStransistor 278 and the first NMOS transistor 274 is turned on greaterthan the second NMOS transistor 278. When resistive change element O01has a high resistive state, the voltage VS237 has a voltage levelgreater than a voltage level of the voltage VS247, the gate voltage ofthe first PMOS transistor 272 is less than the gate voltage of thesecond PMOS transistor 276 and the first PMOS transistor 272 is turnedon greater than the second PMOS transistor 276. Additionally, when theresistive change element O01 has a high resistive state, the gatevoltage of the first NMOS transistor 274 is less than the gate voltageof the second NMOS transistor 278 and the first NMOS transistor 274 isturned on less than the second NMOS transistor 278. During comparing thevoltage VGB2(0) on the global bit line GB2(0) with the voltage on thereference line RL2, current generally does not flow through the latchdevice 270 because the first PMOS transistor 262 of the power controldevice 260 and the first NMOS transistor 264 of the power control device260 are turned off. The first PMOS transistor 262 of the power controldevice 260 is turned off because the first power on signal PONB has ahigh level and the first NMOS transistor 264 of the power control device260 is turned off because the second power on signal NON has a lowlevel.

As shown in FIG. 2B, at the conclusion of comparing the voltage VGB2(0)on the global bit line GB2(0) with the voltage on the reference lineRL2, the initialization signal INIT transitions to a low level, thecomplementary initialization signal INITB transitions to a high level,the sense amplifier enable signal SAEN transitions to a low level, thefirst power on signal PONB transitions to a low level, and after a smalldelay the second power on signal NON transitions to a high level. Asdiscussed above, when the initialization signal INIT has a high leveland the complementary initialization signal INITB has a low level, thefirst sense amplifier 200 is in an initializing configuration, the firstinput device 210 provides the voltage on the reference line RL2 to thefirst load device 230, and the second input device 220 provides thevoltage on the reference line RL2 to the second input device 240.Additionally, when the first power on signal PONB has a low level, thelatch device 270 is disconnected from the first load device 230 and thesecond load device 240 and the latch device 270 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the system voltage VDD. The latch device270 is disconnected from the first load device 230 by turning off thesecond NMOS transistor 266 of the power control device 260 and the latchdevice 270 is disconnected from the second load device 240 by turningoff the third NMOS transistor 268. The latch device 270 is electricallyconnected to a power supply, a voltage source, a driver circuit, orother device that supplies the system voltage VDD by turning on the PMOStransistor 262 of the power control device 260. The PMOS transistor 262is turned on, the second NMOS transistor 266 is turned off, and thethird NMOS transistor 268 is turned off because the first power onsignal PONB has a low level. Further, when the second power on signalNON has a high level, the latch device 270 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies 0 volts or ground. The latch device 270 iselectrically connected to the power supply, the voltage source, thedriver circuit, or other device that supplies the 0 volts or ground byturning on the first NMOS transistor 264 of the power control device260. The first NMOS transistor 264 is turned on because the second poweron signal NON has a high level.

When comparing the voltage VGB2(0) on the global bit line GB2(0) withthe voltage on the reference line RL2 concludes, the voltage on thefirst output 201, the voltage on the gate terminal of the second PMOStransistor 276, and the voltage on the gate terminal of the second NMOStransistor 278 are approximately equal to the voltage VS237 and thevoltage on the second output 202, the voltage on the gate terminal ofthe first PMOS transistor 272, and the voltage on the gate terminal ofthe first NMOS transistor 274 are approximately equal to the voltageVS247. The voltage difference between the voltage VS237 and the voltageVS247 can be increased by having a small delay between the first poweron signal PONB transitioning to a low level and the second power onsignal NON transitioning to high level. During the small delay, currentcan flow from the power supply, the voltage source, the driver circuit,or other device that supplies the system voltage VDD through the PMOStransistor 262 of the power control device 260 and the first PMOStransistor 272 of the latch device 270 and pull up the voltages on thefirst output 201, the gate terminal of the second PMOS transistor 276,and the gate terminal of the second NMOS transistor 278. Also, duringthe small delay, current can flow from the power supply, the voltagesource, the driver circuit, or other device that supplies the systemvoltage VDD through the PMOS transistor 262 of the power control device260 and the second PMOS transistor 276 of the latch device 270 and pullup the voltages on the second output 202, the gate terminal of the firstPMOS transistor 272, and the gate terminal of the first NMOS transistor274. When the voltage level of the voltage VS237 is less than thevoltage level of the voltage VS247, the first PMOS transistor 272 isturned on less than the second PMOS transistor 276 and the voltages onthe first output 201, the gate terminal of the second PMOS transistor276, and the gate terminal of the second NMOS transistor 278 are pulledup less than the voltages on the second output 202, the gate terminal ofthe first PMOS transistor 272, and the gate terminal of the first NMOStransistor 274 because an amount of current flowing through the firstPMOS transistor 272 is less than an amount of current flowing throughthe second PMOS transistor 276. When the voltage level of the voltageVS237 is greater than the voltage level of the voltage VS247, the firstPMOS transistor 272 is turned on greater than the second PMOS transistor276 and the voltages on the first output 201, the gate terminal of thesecond PMOS transistor 276, and the gate terminal of the second NMOStransistor 278 are pulled up greater than the voltages on the secondoutput 202, the gate terminal of the first PMOS transistor 272, and thegate terminal of the first NMOS transistor 274 because an amount ofcurrent flowing through the first PMOS transistor 272 is greater than anamount of current flowing through the second PMOS transistor 276.Alternatively, the first power on signal PONB transitioning to a lowlevel and the second power on signal NON transitioning to a high levelcan occur at approximately the same time.

After the first power on signal PONB has a low level and the secondpower on signal NON has a high level, the voltages on the first output201, the gate terminal of the second PMOS transistor 276, and the gateterminal of the second NMOS transistor 278 transition to the systemvoltage VDD or 0 volts or ground and the voltages on the second output202, the gate terminal of the first PMOS transistor 272, and the gateterminal of the first NMOS transistor 274 transition to the systemvoltage VDD or 0 volts or ground. When the resistive change element O01has a low resistive state the voltage on the first output 201, the gateterminal of the second PMOS transistor 276, and the gate terminal of thesecond NMOS transistor 278 transition to 0 volts or ground and thevoltages on the second output 202, the gate terminal of the first PMOStransistor 272, and the gate terminal of the first NMOS transistor 274transition to the system voltage VDD because the first PMOS transistor272 is turned on less than the second PMOS transistor 276 and the firstNMOS transistor 274 is turned on greater than the second NMOS transistor278. The voltage on the first output 201 being 0 volts or ground and thevoltage on the second output 202 being the system voltage VDD is storedin the latch device 270 by the first PMOS transistor 272 being turnedoff, the first NMOS transistor 274 being turned on, the second PMOStransistor 276 being turned on, and the second NMOS transistor 278 beingturned off. Additionally, the voltage on the first output 201 isgenerally kept at 0 volts or ground and the voltage on the second output202 is generally kept at the system voltage VDD by the first PMOStransistor 272 being turned off, the first NMOS transistor 274 beingturned on, the second PMOS transistor 276 being turned on, and thesecond NMOS transistor 278 being turned off. Therefore, when resistivechange element O01 has a low resistive state the first sense amplifier200 outputs 0 volts or ground on the first output 201 and the systemvoltage VDD on the second output 202.

When the resistive change element O01 has a high resistive state thevoltage on the first output 201, the gate terminal of the second PMOStransistor 276, and the gate terminal of the second NMOS transistor 278transition to the system voltage VDD and the voltages on the secondoutput 202, the gate terminal of the first PMOS transistor 272, and thegate terminal of the first NMOS transistor 274 transition to 0 volts orground because the first PMOS transistor 272 is turned on greater thanthe second PMOS transistor 276 and the first NMOS transistor 274 isturned on less than the second NMOS transistor 278. The voltage on thefirst output 201 being the system voltage VDD and the voltage on thesecond output 202 being 0 volts or ground is stored in the latch device270 by the first PMOS transistor 272 being turned on, the first NMOStransistor 274 being turned off, the second PMOS transistor 276 beingturned off, and the second NMOS transistor 278 being turned on.Additionally, the voltage on the first output 201 is generally kept thesystem voltage VDD and the voltage on the second output 202 is generallykept 0 volts or ground by the first PMOS transistor 272 being turned on,the first NMOS transistor 274 being turned off, the second PMOStransistor 276 being turned off, and the second NMOS transistor 278being turned on. Therefore, when resistive change element O01 has a highresistive state the first sense amplifier 200 outputs the system voltageVDD on the first output 201 and 0 volts or ground on the second output202.

Referring now to FIGS. 1I-1, 1I-2, and 1I-3, an exemplary DDR compatibleimplementation of the first exemplary architecture for programming andaccessing resistive change elements is illustrated in a simplifiedschematic diagram. The exemplary DDR compatible implementation of thefirst exemplary architecture includes a plurality of global bit linesGB3(0)-GB3(x), a resistive change element array 101 having a pluralityof sections Section A-Section Z, word line driver circuitry 110 a-110 zfor each section, a reference line RL3, a reference line connectioncircuit 120 a-120 z for each section, a plurality of bus lines BL30-BL3x, a keeper circuit 130, a global bit line connection circuit 180, aplurality of write buffer circuits 1500-150 x, a plurality of currentsources 1600-160 x, a capacitor 170, and a plurality of sense amplifiers2000-200 x. The keeper circuit 130 and the capacitor 170 have a similarstructure to the keeper circuit 130 and the capacitor 170 discussedabove with respect to the exemplary implementation of first exemplaryarchitecture for programming and accessing resistive change elements.Therefore, the keeper circuit 130 and the capacitor 170 are notdiscussed in detail with respect to the exemplary DDR compatibleimplementation of the first exemplary architecture.

Each section of the plurality of sections Section A-Section Z has thesame structure as Section A, and thus, the discussion below of Section Ais applicable to each section in the plurality of sections SectionA-Section Z. Additionally, the numbering convention for the plurality ofsections Section A-Section Z is for convenience of description and easeof distinction between groups of features and is not intended to limitthe number of sections in the plurality of sections Section A-Section Z.

Section A includes a plurality of resistive change elements E00 a-Oxya,a plurality of even bit lines Bea(0)-Bea(x), a plurality of odd bitlines Boa(0)-Boa(x), a plurality of word lines Wa(0)-Wa(y), a pluralityof even selection devices Nea0-Neax, and a plurality of odd selectiondevices Noa0-Noax. Each resistive change element in the plurality ofresistive change elements E00 a-Oxya includes a bottom electrode BE, aresistive change material, and a top electrode TE. A nanotube fabricserves as the resistive change material. The resistive change materialis shown in FIG. 1I-1 using diagonal lines between the bottom electrodeBE and the top electrode TE. The bottom electrode BE is in contact withthe resistive change material and the top electrode TE is in contactwith the resistive change material. Alternatively, each resistive changeelement in the plurality of resistive change elements E00 a-Oxya caninclude at least one intervening layer located between the bottomelectrode BE and the resistive change material, at least one interveninglayer located between the resistive change material and the topelectrode TE, or at least one intervening layer located between thebottom electrode BE and the resistive change material and at least oneintervening layer located between the resistive change material and thetop electrode TE. Alternatively, the bottom electrode BE can be omittedfrom each resistive change element in the plurality of resistive changeelements E00 a-Oxya, the top electrode TE can be omitted from the eachresistive change element in the plurality of resistive change elementsE00 a-Oxya, or the bottom electrode BE and the top electrode TE can beomitted from each resistive change element in the plurality of resistivechange elements E00 a-Oxya. Alternatively, the resistive change materialcan comprise another resistive change material such as other carbonallotropes such as Buckyballs, graphene flakes, nanocapsules, andnanohorns. It is noted that while the present disclosure provides someexamples of resistive change elements including nanotube fabrics orother carbon allotropes as resistive change materials the presentdisclosure is not limited to resistive change elements includingnanotube fabrics or other carbon allotropes as resistive changematerials and that the present disclosure is applicable to other typesof resistive change elements such as phase change, metal oxide, andsolid electrolyte.

Each resistive change element of the plurality of resistive changeelements E00 a-Oxya can be adjusted (programmed) between twonon-volatile resistive states, a low resistive state, for example aresistance on the order of 1MΩ (corresponding, typically, to a logic‘1,’ a SET state), and a high resistive state, for example a resistanceon the order of 101\40 (corresponding, typically, to a logic ‘0,’ aRESET state), by applying electrical stimuli to the resistive changeelement. When the resistive change elements are adjusted (programmed)between resistive states in a bidirectional manner, the resistive changeelements are adjusted (programmed) between resistive states byelectrical stimuli that cause current flow in different directionsrelative to the top electrodes TE and the bottom electrodes BE. When theresistive change elements are adjusted (programmed) between resistivestates in a bidirectional manner, the resistive change elements can beadjusted to the low resistive state by an electrical stimulus thatcauses current flow from the bottom electrode BE to the top electrode TEand can be adjusted to the high resistive state by an electricalstimulus that causes current flow from the top electrode TE to thebottom electrode BE. When the resistive change elements are adjusted(programmed) between resistive states in a unidirectional manner, theresistive change elements are adjusted (programmed) between resistivestates by electrical stimuli that cause current flow in the samedirection relative to the top electrodes TE and the bottom electrodesBE. When the resistive change elements are adjusted (programmed) betweenresistive states in a unidirectional manner, the resistive changeelements can be adjusted between the low resistive state and the highresistive state by electrical stimuli that cause current flow in thesame direction relative to the top electrode TE and the bottom electrodeBE. Alternatively, each resistive change element of the plurality ofresistive change elements E00 a-Oxya can be adjusted (programmed)between more than two non-volatile resistive states, where eachnon-volatile resistive state corresponds with a different resistancevalue, by applying electrical stimuli to the resistive change elements.

As shown in FIG. 1I-1, the even bit lines of the plurality of even bitlines Bea(0)-Bea(x) may be arranged generally along the Y-axis andgenerally in parallel with respect to each other, the odd bit lines ofthe plurality of odd bit lines Boa(0)-Boa(x) may be arranged generallyalong the Y-axis and generally in parallel with respect to each other,and the global bit lines of the plurality of global bit linesGB3(0)-GB3(x) may be arranged generally along the Y-axis and generallyin parallel with respect to each other. Also, as shown in FIG. 1I-1, theeven bit lines of the plurality of even bit lines Bea(0)-Bea(x), the oddbit lines of the plurality of odd bit lines Boa(0)-Boa(x), and theglobal bit lines of the plurality of global bit lines GB3(0)-GB3(x) maybe arranged generally in parallel with respect to each other.Additionally, as shown in FIG. 1I-1, the word lines of the plurality ofword lines Wa(0)-Wa(y) may be arranged generally along the X-axis andgenerally in parallel with respect to each other. It is noted that theeven bit lines Bea(0)-Bea(x) are described as being generally inparallel with respect to each other, the odd bit lines Boa(0)-Boa(x) aredescribed as being generally in parallel with respect to each other, theglobal bit lines GB3(0)-GB3(x) are described as being generally inparallel with respect to each other, and the word lines Wa(0)-Wa(y) aredescribed as being generally in parallel with respect to each other toallow for variations from exactly parallel due to the fabricationprocess. It is also noted that the even bit lines Bea(0)-Bea(x), the oddbit lines Boa(0)-Boa(x), and the global bit lines GB3(0)-GB3(x) aredescribed as being generally in parallel with respect to each other toallow for variations from exactly parallel due to the fabricationprocess.

Section A has one even bit line and one odd bit line per column and oneword line per row. The numbering convention for the plurality of evenbit lines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x)reflects that section A has one even bit line and one odd bit line percolumn. The numbering convention for the plurality of even bit linesBea(0)-Bea(x) begins with the letter B indicating the array line is abit line followed by the letter e indicating the bit line is an even bitline followed by the letter a indicating the bit line is in section Afollowed by a column number in parentheses. The numbering convention forthe plurality of odd bit lines Boa(0)-Boa(x) begins with the letter Bindicating the array line is a bit line followed by the letter oindicating the bit line is an odd bit line followed by the letter aindicating the bit line is in section A followed by a column number inparentheses. The numbering convention for the plurality of word linesWa(0)-Wa(y) begins with the letter W indicating the array line is a wordline followed by the letter a indicating the word line is in section Afollowed by a row number in parentheses. The numbering convention forthe global bit lines GB3(0)-GB3(x) begins with the letters and numberGB3 indicating the line is a global bit line followed by a column numberin parentheses. Alternatively, section A may have at least one columnwith one even bit line and at least one column with one even bit lineand one odd bit line, at least one column with one odd bit line and atleast one column with one even bit line and one odd bit line, or atleast one column with one even bit line, at least one column with oneodd bit line, and at least one column with one even bit line and one oddbit line. It is noted that for discussion purposes the number 0 isconsidered to be an even number. Also, references to “even” and “odd”herein are for convenience of description and ease of distinctionbetween groups of features and are not intended to be rigidcharacterizations, insofar as a same architecture could relabel the“even” structures as “odd” structures and vice versa.

As shown in FIG. 1I-1, the word lines of the plurality of word linesWa(0)-Wa(y) may be generally orthogonal to the even bit lines of theplurality of even bit lines Bea(0)-Bea(x), the odd bit lines of theplurality of odd bit lines Boa(0)-Boa(x), and the global bit lines ofthe plurality of global bit lines GB3(0)-GB3(x). Additionally, as shownin FIG. 1I-1, the resistive change elements of the plurality ofresistive change elements E00 a-Oxya may be located where a word line ofthe plurality of word lines Wa(0)-Wa(y) crosses an even bit line of theplurality of even bit lines Bea(0)-Bea(x) and where a word line of theplurality of word lines Wa(0)-Wa(y) crosses an odd bit line of theplurality of odd bit lines Boa(0)-Boa(x). Resistive change elementslocated where a word line of the plurality of word lines Wa(0)-Wa(y)crosses an even bit line of the plurality of even bit linesBea(0)-Bea(x) have top electrodes TE in electrical communication withword lines of the plurality of word lines Wa(0)-Wa(y) and bottomelectrodes BE in electrical communication with even bit lines of theplurality of even bit lines Bea(0)-Bea(x). Resistive change elementslocated where a word line of the plurality of word lines Wa(0)-Wa(y)crosses an odd bit line of the plurality of odd bit lines Boa(0)-Boa(x)have top electrodes TE in electrical communication with word lines ofthe plurality of word lines Wa(0)-Wa(y) and bottom electrodes BE inelectrical communication with odd bit lines in the plurality of odd bitlines Boa(0)-Boa(x).

The arrangement of the plurality of resistive change elements E00 a-Oxyareflects section A having one even bit line and one odd bit line percolumn and one word line per row. As shown in FIG. 1I-1, the pluralityof resistive change elements E00 a-Oxya is arranged in a N×M matrix,where N is a positive integer that is a multiple of 2 and M is apositive integer. The numbering convention for the plurality ofresistive change elements E00 a-Oxya includes the letter E indicatingthe resistive change element is in electrical communication with an evenbit line or the letter O indicating the resistive change element is inelectrical communication with an odd bit line followed by a columnnumber followed by a row number followed by the letter a indicating theresistive change element is in Section A. It is noted that although theplurality of resistive change elements E00 a-Oxya is arranged in arectangular matrix, the plurality of resistive change elements E00a-Oxya can be arranged in other layouts such as a square matrix. It isalso noted that a plurality of resistive change elements in a differentsection is not limited to having the same number of resistive changeelements and the same layout as the plurality of resistive changeelements E00 a-Oxya in Section A and that a plurality of resistivechange elements in a different section can have a number of resistivechange elements that differs from the number of resistive changeelements in the plurality of resistive change elements E00 a-Oxya inSection A and/or a layout that differs from the layout of the pluralityof resistive change elements E00 a-Oxya in Section A.

As shown in FIG. 1I-1, even bit lines of the plurality of even bit linesBea(0)-Bea(x) and global bit lines of the plurality of global bit linesGB3(0)-GB3(x) having the same column number are in electricalcommunication with the same even selection device of the plurality ofeven selection devices Nea0-Neax. The plurality of even selectiondevices Nea0-Neax are NMOS transistors having drain terminals, gateterminals, and source terminals. The drain terminals of the plurality ofeven selection devices Nea0-Neax are in electrical communication withthe plurality of global bit lines GB3(0)-GB3(x). The gate terminals ofthe plurality of even selection devices Nea0-Neax are in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller. The source terminals of the plurality of evenselection devices Nea0-Neax are in electrical communication with theplurality of even bit lines Bea(0)-Bea(x). The numbering convention forthe plurality of even selection devices Nea0-Neax includes the letter eindicating the even selection device is in electrical communication withan even bit line followed by the letter a indicating the even selectiondevice is in section A followed by a column number. Alternatively, theeven selection devices Nea0-Neax can be other types of field effecttransistors, such as carbon nanotube field effect transistors (CNTFETs),SiGE FETs, fully-depleted silicon-on-insulator FETs, or multiple gatefield effect transistors such as FinFETs. It is noted that when fieldeffect transistors that do not require a semiconductor substrate areused this enables the field effect transistors to be fabricated oninsulator material, and additionally, enables the field effecttransistors to be stacked to reduce the amount of chip area consumed bythe plurality of even selection devices Nea0-Neax.

Also, as shown in FIG. 1I-1, odd bit lines of the plurality of odd bitlines Boa(0)-Boa(x) and global bit lines of the plurality of global bitlines GB3(0)-GB3(x) having the same column number are in electricalcommunication with the same odd selection device of the plurality of oddselection devices Noa0-Noax. The plurality of odd selection devicesNoa0-Noax are NMOS transistors having drain terminals, gate terminals,and source terminals. The drain terminals of the plurality of oddselection devices Noa0-Noax are in electrical communication with theplurality of global bit lines GB3(0)-GB3(x). The gate terminals of theplurality of odd selection devices Noa0-Noax are in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller. The source terminals of the plurality of oddselection devices Noa0-Noax are in electrical communication with theplurality of odd bit lines Boa(0)-Boa(x). The numbering convention forthe plurality of odd selection devices Noa0-Noax includes the letter oindicating the odd selection device is in electrical communication withan odd bit line followed by the letter a indicating the odd selectiondevice is in section A followed by a column number. Alternatively, theodd selection devices Noa0-Noax can be other types of field effecttransistors, such as carbon nanotube field effect transistors (CNTFETs),SiGE FETs, fully-depleted silicon-on-insulator FETs, or multiple gatefield effect transistors such as FinFETs. It is noted that when fieldeffect transistors that do not require a semiconductor substrate areused this enables the field effect transistors to be fabricated oninsulator material, and additionally, enables the field effecttransistors to be stacked to reduce the amount of chip area consumed bythe plurality of odd selection devices Noa0-Noax.

Each of the word line driver circuitries 110 a-110 z has the samestructure as the word line driver circuitry 110 a for Section A, andthus, the discussion below of the word line driver circuitry 110 a forSection A is applicable to each of the word line driver circuitries 110a-110 z. The numbering convention for the word line driver circuitries110 a-110 z reflects the section of the resistive change element arraythat a word line driver circuitry corresponds with because the lastreference character for each word line driver circuitry refers to thesection of the resistive change element array.

The word line driver circuitry for Section A includes a first NMOStransistor 110 pa, a second NMOS transistor 111 pa, a plurality of wordline driver circuits 110 da-11 yda, and a plurality of sink transistors110 sa-11 ysa. The first NMOS transistor 110 pa has a drain terminal, agate terminal, and a source terminal, and the second NMOS transistor 111pa has a drain terminal, a gate terminal, and a source terminal. Thedrain terminal of the first NMOS transistor 110 pa is in electricalcommunication with the plurality of word line driver circuits 110 da-11yda, the gate terminal of the first NMOS transistor 110 pa is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive a signal S0 a forcontrolling current flow through the first NMOS transistor 110 pa, andthe source terminal of the first NMOS transistor 110 pa is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the system voltage VDD. The drain terminalof the second NMOS transistor 111 pa is in electrical communication withthe plurality of word line driver circuits 110 da-11 yda and thereference line connection circuit 120 a for Section A, the gate terminalof the second NMOS transistor 111 pa is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive a signal S1 a for controlling current flow through the secondNMOS transistor 111 pa, and the source terminal of the second NMOStransistor 111 pa is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies theinhibit voltage VINH.

Each word line driver circuit in the plurality of word line drivercircuits 110 da-11 yda has an input terminal, an output terminal, afirst power terminal, and a second power terminal. The input terminalsof the word line driver circuits in the plurality of word line drivercircuits 110 da-11 yda are in electrical communication with controllogic, such as a processor, a controller, and a microcontroller. Theoutput terminals of the word line driver circuits in the plurality ofword line driver circuits 110 da-11 yda are in electrical communicationwith word lines in the plurality of word lines Wa(0)-Wa(y) with thethird reference character for each word line driver circuit indicatingthe word line that word line driver circuit is in electricalcommunication with because the third reference character for each wordline driver circuit refers to a row number. The first power terminals ofthe word line driver circuits in the plurality of word line drivercircuits 110 da-11 yda are in electrical communication with the drainterminal of the first NMOS transistor 110 pa. The second power terminalsof the word line driver circuits in the plurality of word line drivercircuits 110 da-11 yda are in electrical communication with the drainterminal of the second NMOS transistor 111 pa.

The plurality of word line driver circuits 110 da-11 yda receive aplurality of signals ITE0 a-ITEya for operating the plurality of wordline driver circuits 110 da-11 yda. The control logic supplies theplurality of signals ITE0 a-ITEya. The plurality of word line drivercircuits 110 da-11 yda receive the system voltage VDD on the first powerterminals when the first NMOS transistor 110 pa is turned on and do notreceive a voltage on the first power terminals when the first NMOStransistor 110 pa is turned off. The plurality of word line drivercircuits 110 da-11 yda receive the inhibit voltage VINH on the secondpower terminals when the second NMOS transistor 111 pa is turned on anddo not receive a voltage on the second power terminals when the secondNMOS transistor 111 pa is turned off. When the first NMOS transistor 110pa and the second NMOS transistor 111 pa are turned on each word linedriver circuit in the plurality of word line driver circuits 110 da-11yda supplies a voltage based on the signal in the plurality of signalsITE0 a-ITEya received by that word line driver circuit. For example,when the first NMOS transistor 110 pa and the second NMOS transistor 111pa are turned on and the word line driver circuit 110 da receives asignal ITE0 a having a low level the word line driver circuit 110 dasupplies the system voltage VDD and when the first NMOS transistor 110pa and the second NMOS transistor 111 pa are turned on and the word linedriver circuit 110 da receives a signal ITE0 a having a high level theword line driver circuit 110 da supplies the inhibit voltage VINH. Whenone of the first NMOS transistor 110 pa and the second NMOS transistor111 pa is turned on and one of the first NMOS transistor 110 pa and thesecond NMOS transistor 111 pa is turned off each word line drivercircuit in the plurality of word line driver circuits 110 d-11 ydsupplies a voltage or does not supply a voltage based on the signal inthe plurality of signals ITE0 a-ITEya received by that word line drivercircuit. For example, when the first NMOS transistor 110 pa is turnedoff and the second NMOS transistor 111 pa is turned on and the word linedriver circuit 110 da receives a signal ITE0 a having a low level theword line driver circuit 110 da does not supply a voltage and when thefirst NMOS transistor 110 pa is turned off and the second NMOStransistor 111 pa is turned on and the word line driver circuit 110 dareceives a signal ITE0 a having a high level the word line drivercircuit 110 da supplies the inhibit voltage VINH. It is noted that, asdiscussed below, the inhibit voltage VINH is applied to a top of aresistive change element and the inhibit voltage VINH is applied to abottom of the resistive change element to provide a neutral voltagecondition. It is also noted that the inhibit voltage VINH can have avoltage level of VDD/2 (half of the system voltage VDD) for example,however, the inhibit voltage is not limited to a voltage of VDD/2 andthat a circuit designer can select other voltages that may deviatesomewhat from VDD/2 for the inhibit voltage VINH.

The plurality of sink transistors 110 sa-11 ysa are NMOS transistorshaving drain terminals, gate terminals, and source terminals. The drainterminals of the plurality of sink transistors 110 sa-11 ysa are inelectrical communication with the plurality of word lines Wa(0)-Wa(y)with the third reference character for each sink transistor indicatingthe word line that sink transistor is in electrical communication withbecause the third reference character for each sink transistor refers toa row number. The gate terminals of the plurality of sink transistors110 sa-11 ysa are in electrical communication with control logic, suchas a processor, a controller, and a microcontroller. The sourceterminals of the plurality of sink transistors 110 sa-11 ysa are inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The pluralityof sink transistors 110 sa-11 ysa receive a plurality of signals SK0a-SKya for controlling current flow through the plurality of sinktransistors 110 sa-11 ysa. The control logic supplies the plurality ofsignals SK0 a-SKya. Alternatively, the sink transistors 110 sa-11 ysacan be other types of field effect transistors, such as carbon nanotubefield effect transistors (CNTFETs), SiGE FETs, fully-depletedsilicon-on-insulator FETs, or multiple gate field effect transistorssuch as FinFETs. It is noted that when field effect transistors that donot require a semiconductor substrate are used this enables the fieldeffect transistors to be fabricated on insulator material, andadditionally, enables the field effect transistors to be stacked toreduce the amount of chip area consumed by the plurality of sinktransistors 110 sa-11 ysa.

Each of the reference line connection circuits 120 a-120 z has the samestructure as the reference line connection circuit 120 a for Section A,and thus, the discussion below of the reference line connection circuit120 a for Section A is applicable to each of the reference lineconnection circuits 120 a-120 z. The numbering convention for thereference line connection circuits 120 a-120 z reflects the section ofthe resistive change element array that a reference line connectioncircuit corresponds with because the last reference character for eachreference line connection circuit refers to the section of the resistivechange element array.

The reference line connection circuit 120 a includes a first NMOStransistor 121 a having a drain terminal, a gate terminal, and a sourceterminal and a second NMOS transistor 122 a having a drain terminal, agate terminal, and a source terminal. The drain terminal of the firstNMOS transistor 121 a is in electrical communication with the referenceline RL3, the gate terminal of the first NMOS transistor 121 a is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, and the source terminal of the firstNMOS transistor 121 a is in electrical communication with the word linedriver circuitry 110 a. The drain terminal of the second NMOS transistor122 a is in electrical communication with the reference line RL3, thegate terminal of the second NMOS transistor 122 a is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, and the source terminal of the second NMOS transistor122 a is in electrical communication with the word line driver circuitry110 a. The first NMOS transistor 121 a receives a signal SSELea forcontrolling current flow through the first NMOS transistor 121 a and theplurality of even selection devices Nea0-Neax. The second NMOStransistor 122 a receives a signal SSELoa for controlling current flowthrough the second NMOS transistor 122 a and the plurality of oddselection devices Noa0-Noax. The control logic supplies the signalSSELea and the signal SSELoa. Alternatively, the source terminal of thefirst NMOS transistor 121 a and the source terminal of the second NMOStransistor 122 a may be in electrical communication a power supply, avoltage source, a driver circuit, or other device that supplies theinhibit voltage VINH. Alternatively, the first NMOS transistor 121 a andthe second NMOS transistor 122 a can be other types of field effecttransistors, such as carbon nanotube field effect transistors (CNTFETs),SiGE FETs, fully-depleted silicon-on-insulator FETs, or multiple gatefield effect transistors such as FinFETs. It is noted that when fieldeffect transistors that do not require a semiconductor substrate areused this enables the field effect transistors to be fabricated oninsulator material, and additionally, enables the field effecttransistors to be stacked to reduce the amount of chip area consumed bythe first NMOS transistor 121 a and the second NMOS transistor 122 a.

The global bit line connection circuit 180 includes a plurality of PMOStransistors 180 g-18 xg having drain terminals, gate terminals, andsource terminals. The numbering convention for the plurality of PMOStransistors 180 g-18 xg includes a column number as the next to lastreference character, the numbering convention for the plurality of buslines BL30-BL3 x includes a column number as the last referencecharacter, and as discussed above the numbering convention for theplurality of global bit lines GB3(0)-GB3(x) begins with letters andnumber GB3 indicating the line is a global bit line followed by a columnnumber in parentheses. The drain terminals of the plurality of PMOStransistors 180 g-18 xg are in electrical communication with bus linesBL30-BL3 x having the same column numbers. The gate terminals of theplurality of PMOS transistors 180 g-18 xg are in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller. The source terminals of the plurality of PMOStransistors 180 g-18 xg are in electrical communication with global bitlines GB3(0)-GB3(x) having the same column number. The plurality of PMOStransistors 180 g-18 xg receive a signal CDO for controlling currentflow through the plurality of PMOS transistors 180 g-18 xg. The controllogic supplies the signal CDO. Alternatively, the PMOS transistors 180g-18 xg can be other types of field effect transistors, such as carbonnanotube field effect transistors (CNTFETs), SiGE FETs, fully-depletedsilicon-on-insulator FETs, or multiple gate field effect transistorssuch as FinFETs. It is noted that when field effect transistors that donot require a semiconductor substrate are used this enables the fieldeffect transistors to be fabricated on insulator material, andadditionally, enables the field effect transistors to be stacked toreduce the amount of chip area consumed by the plurality of PMOStransistors 180 g-18 xg.

Each write buffer circuit of the plurality of write buffer circuits1500-150 x has the same structure as the write buffer circuit 1500, andthus, the discussion below of the write buffer circuit 1500 isapplicable to each write buffer circuit of the plurality of write buffercircuits 1500-150 x. The numbering convention for the plurality of writebuffer circuits 1500-150 x includes a column number as the lastreference character and a write buffer circuit corresponds with a globalbit line having the same column number. Additionally, the numberingconventions for write set signals WR00-WR0 x and write reset signalsWR10-WR1 x received by the plurality of write buffer circuits 1500-150 xinclude a column number as the last reference character and each writebuffer circuit receives a write set signal and a write reset signalhaving the same column number as that write buffer circuit.

The write buffer circuit 1500 has a first input terminal, a second inputterminal, an output terminal, a first power terminal, and a second powerterminal. The first input terminal and the second input terminal of thewrite buffer circuit 1500 are in electrical communication with controllogic, such as a processor, a controller, and a microcontroller. Theoutput terminal of the write buffer circuit 1500 is in electricalcommunication with the bus line BL30 having the same column number asthe write buffer circuit 1500. The first power terminal of the writebuffer circuit 1500 is in electrical communication with a power supply,a voltage source, a driver circuit, or other device that supplies asystem voltage VDD. The second power terminal of the write buffercircuit 1500 is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies 0 voltsor ground. The write buffer circuit 1500 receives a write set signalWR00 on the first input terminal and a write reset signal WR10 on thesecond input terminal. The control logic supplies the write set signalWR00 and the write reset signal WR10. When the write buffer circuit 1500receives the write set signal WR00 having a low level and the writereset signal WR10 having a low level the write buffer circuit 1500supplies the system voltage VDD. When the write buffer circuit 1500receives the write set signal WR00 having a high level and the writereset signal WR10 having a high level the write buffer circuit 1500supplies 0 volts or ground. When the write buffer circuit 1500 receivesthe write set signal WR00 having a high level and the write reset signalWR10 having a low level the write buffer circuit 1500 does not supply avoltage. Although, not shown in FIG. 1I-3, the output terminal of thewrite buffer circuit 1500 may be in electrical communication with thebus line BL30 through a resistor for limiting current flow from thewrite buffer circuit 1500.

Alternatively, the first power terminal of the write buffer circuit 1500may be in electrical communication with a field effect transistor andthe field effect transistor may be in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD and/or the second power terminal of thewrite buffer circuit 1500 may be in electrical communication with afield effect transistor and the field effect transistor may be inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground.

Each current source of the plurality of current sources 1600-160 x hasthe same structure as the current source 1600, and thus, the discussionbelow of the current source 1600 is applicable to each current source ofthe plurality of current sources 1600-160 x. The numbering conventionfor the plurality of current sources 1600-160 x includes a column numberas the last reference character and a current source corresponds with aglobal bit line having the same column number. Additionally, thenumbering conventions for current source enable signals CSENO-CSENx andcurrent source bias current signals CSBO-CSBx received by the pluralityof current sources 1600-160 x include column numbers as the lastreference characters and each current source receives a current sourceenable signal and a current source bias current signal having the samecolumn number as that current source.

The current source 1600 includes a first NMOS transistor 1610 have adrain terminal, a gate terminal, and a source terminal and a second NMOStransistor 1620 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 1610 is inelectrical communication with the bus line BL30 having the same columnnumber as the current source 1600. The gate terminal of the first NMOStransistor 1610 is in electrical communication with control logic, suchas a processor, a controller, and a microcontroller, to receive acurrent source enable signal CSENO. The source terminal of the firstNMOS transistor 1610 is in electrical communication with the drainterminal of the second NMOS transistor 1620. The drain terminal of thesecond NMOS transistor 1620 is in electrical communication with thesource terminal of the first NMOS transistor 1610. The gate terminal ofthe second NMOS transistor 1620 is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive a current source bias current signal CSBO. The sourceterminal of the second NMOS transistor 1620 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies 0 volts or ground. The control logicsupplies the current source enable signal CSENO to enable and disablethe current source 1600 and the current source bias current signal CSBOto set the amount of current sunk by the current source 1600. Thecurrent source 1600 may be set to sink different amounts of current fordifferent operations of a resistive change element. For example, thecurrent source 1600 may be set to sink an amount of current for a READoperation, an amount of current for a SET VERIFY operation, and anamount of current for a RESET VERIFY operation.

Each sense amplifier of the plurality of sense amplifiers 2000-200 x hasthe same structure as the first sense amplifier 200 discussed above. Thenumbering convention for the plurality of sense amplifiers 2000-200 xincludes a column number as the last reference character and a senseamplifier corresponds with a global bit line having the same columnnumber. For ease of illustration, FIG. 1I-3 shows a simplified diagramof each sense amplifier of the plurality of sense amplifiers 2000-200 xhaving two input terminals in electrical communication with thereference line RL3, one input terminal in electrical communication withthe bus line having the same column number as that sense amplifier, andtwo output terminals. The two output terminals of each sense amplifierof the plurality of sense amplifiers 2000-200 x can be in electricalcommunication with a bus, a buffer, a level shift circuit, a testcircuit, or control logic such as a processor, a controller, and amicrocontroller.

The exemplary DDR compatible implementation of the first exemplaryarchitecture shown in FIGS. 1I-1, 1I-2, and 1I-3 provides forPROGRAMMING operations of multiple resistive change elements to the sameresistive state at the same time and READ operations, SET VERIFYoperations, and RESET VERIFY operations of multiple resistive changeelements at the same time. For example, PROGRAMMING operations to adjustresistive states of even resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 can be performed at the same time. For example,PROGRAMMING operations to adjust resistive states of NUM even resistivechange elements in electrical communication with a word line in asection of the resistive change element array 101 can be performed atthe same time, where NUM is a number of resistive change elementsgreater than one and less than the total number of even resistive changeelements in electrical communication with the word line. For example,PROGRAMMING operations to adjust resistive states of odd resistivechange elements in electrical communication with a word line in asection of the resistive change element array 101 can be performed atthe same time. For example, PROGRAMMING operations to adjust resistivestates of NUM odd resistive change elements in electrical communicationwith a word line in a section of the resistive change element array 101can be performed at the same time, where NUM is a number of resistivechange elements greater than one and less than the total number of oddresistive change elements in electrical communication with the wordline. For example, READ operations, SET VERIFY operations, and RESETVERIFY operations of even resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 can be performed at the same time. For example, READoperations, SET VERIFY operations, and RESET VERIFY operations of NUMeven resistive change elements in electrical communication with a wordline in a section of the resistive change element array 101 can beperformed at the same time, where NUM is a number of resistive changeelements greater than one and less than the total number of evenresistive change elements in electrical communication with the wordline. For example, READ operations, SET VERIFY operations, and RESETVERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 can be performed at the same time. For example, READoperations, SET VERIFY operations, and RESET VERIFY operations of NUModd resistive change elements in electrical communication with a wordline in a section of the resistive change element array 101 can beperformed at the same time, where NUM is a number of resistive changeelements greater than one and less than the total number of oddresistive change elements in electrical communication with the wordline.

Additionally, the exemplary DDR compatible implementation of the firstexemplary architecture shown in FIGS. 1I-1, 1I-2, and 1I-3 provides forPROGRAMMING operations, READ operations, SET VERIFY operations, andRESET VERIFY operations of one resistive change element at a time. Forexample, PROGRAMMING operations, READ operations, SET VERIFY operations,and RESET VERIFY operations of one resistive change element at a timemay be performed in a test mode of the exemplary DDR compatibleimplementation of the first exemplary architecture. PROGRAMMINGoperations, READ operations, SET VERIFY operations, and RESET VERIFYoperations of one resistive change element at a time in the exemplaryDDR compatible implementation of the first exemplary architecture can beperformed in a similar manner to PROGRAMMING operations, READoperations, SET VERIFY operations, and RESET VERIFY operations ofresistive change elements in the exemplary implementation of the firstexemplary architecture shown in FIGS. 1D-1 and 1D-2 and discussed above.Therefore, PROGRAMMING operations, READ operations, SET VERIFYoperations, and RESET VERIFY operations of one resistive change elementat a time in the exemplary DDR compatible implementation of the firstexemplary architecture are not discussed in detail below. It is notedthat the exemplary DDR compatible implementation of the first exemplaryarchitecture may be used with interface circuitry tailored for otherSRAM interfaces so that the exemplary DDR compatible implementation ofthe first exemplary architecture is compatible with other SRAMinterfaces.

PROGRAMMING operations to adjust resistive states of odd resistivechange elements in electrical communication with a word line in asection of the resistive change element array 101 are discussed belowwith respect to FIGS. 1J-1, 1J-2, and 1J-3 that show current flow duringa PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states and FIGS. 1K-1, 1K-2, and 1K-3 thatshow current flow during a PROGRAMMING operation to adjust resistivestates of odd resistive change elements in electrical communication withword line Wa(1) in Section A to high resistive states. READ operations,SET VERIFY operations, and RESET VERIFY operations of odd resistivechange elements in electrical communication with a word line in asection of the resistive change element array 101 are discussed belowwith respect to FIGS. 1L-1, 1L-2, and 1L-3 that show current flow duringa READ operation of odd resistive change elements in electricalcommunication with word line Wa(1). It is noted that PROGRAMMINGoperations to adjust resistive states of odd resistive change elementsin electrical communication with a word line in a section of resistivechange element array 101 and PROGRAMMING operations to adjust resistivestates of even resistive change elements in electrical communicationwith a word line in a section of resistive change element array 101 canbe performed in a similar manner to PROGRAMMING operations to adjustresistive states of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A. It is additionallynoted that READ operations, SET VERIFY operations, and RESET VERIFYoperations of odd resistive change elements in electrical communicationwith a word line in a section of resistive change element array 101 andREAD operations, SET VERIFY operations, and RESET VERIFY operations ofeven resistive change elements in electrical communication with a wordline in a section of resistive change element array 101 can be performedin a similar manner to the READ operations, SET VERIFY operations, andRESET VERIFY operations of odd resistive change elements in electricalcommunication with word line Wa(1).

Referring now to FIGS. 1J-1, 1J-2, and 1J-3, a PROGRAMMING operation toadjust resistive states of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A to low resistive statesstarts, as similarly discussed above in step 302 of the flow chart 300,by providing neutral voltage conditions for the plurality of resistivechange elements E00 a-Oxya in Section A and the plurality of resistivechange elements E00 z-Oxyz in Section Z. The neutral voltage conditionsare provided for the plurality of resistive change elements E00 a-Oxyain section A by floating the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) and applying theinhibit voltage VINH to the plurality of word lines Wa(0)-Wa(y) with theplurality of even bit lines Bea(0)-Bea(x) and the plurality of odd bitlines Boa(0)-Boa(x) floating so that voltages approximately equal to theinhibit voltage VINH are applied to the top electrodes and the bottomelectrodes of the resistive change elements in the plurality ofresistive change elements E00 a-Oxya. Floating a line refers toelectrically connecting the line such that a voltage on the line existsdue to a line capacitance of the line. The plurality of even bit linesBea(0)-Bea(x) are floated by disconnecting the plurality of even bitlines Bea(0)-Bea(x) from the plurality of global bit lines GB3(0)-GB3(x)by turning off the plurality of even selection devices Nea0-Neax inSection A. The plurality of even selection devices Nea0-Neax are turnedoff by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELea having a low level. Theplurality of odd bit lines Boa(0)-Boa(x) are floated by disconnectingthe plurality of odd bit lines Boa(0)-Boa(x) from the plurality ofglobal bit lines GB3(0)-GB3(x) by turning off the plurality of oddselection devices Noa0-Noax in Section A. The plurality of odd selectiondevices Noa0-Noax are turned off by control logic, such as a processor,a controller, and a microcontroller, supplying a signal SSELoa having alow level. It is noted that control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELea having alow level and a signal SSELoa having a low level also turns off thefirst NMOS transistor 121 a and the second NMOS transistor 122 a of thereference line connection circuit 120 a for Section A.

The inhibit voltage VINH is applied to the plurality of word linesWa(0)-Wa(y) by the word line driver circuitry 110 a for Section Adriving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110da-11 yda do not receive a voltage on the first power terminals becausethe first NMOS transistor 110 pa is turned off by control logic, such asa processor, a controller, and a microcontroller, supplying the signalS0 a having a low level and receive the inhibit voltage VINH on thesecond power terminals because the second NMOS transistor 111 pa isturned on by the control logic supplying the signal S1 a having a highlevel. The plurality of word line driver circuits 110 da-11 yda supplythe inhibit voltage VINH based on the plurality of signals ITE0 a-ITEyasupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sa-11 ysa areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 a-SKya have lowlevels.

Driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating causesvoltages on the plurality of word lines Wa(0)-Wa(y), voltages on theplurality of even bit lines Bea(0)-Bea(x), and voltages on the pluralityof odd bit lines Boa(0)-Boa(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bea(0)-Bea(x)and voltages on the plurality of odd bit lines Boa(0)-Boa(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wa(0)-Wa(y) through the plurality ofresistive change elements E00 a-Oxya into the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x).The inhibit voltage VINH exists on the plurality of even bit linesBea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x) due toline capacitances because the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) are floating. Thus,driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 a-Oxya.Additionally, driving voltages on the plurality of word linesWa(0)-Wa(y) to the inhibit voltage VINH with the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 a-Oxya to be approximately 0volts.

The neutral voltage conditions are provided for the plurality ofresistive change elements E00 z-Oxyz in section Z by floating theplurality of even bit lines Bez(0)-Bez(x) and the plurality of odd bitlines Boz(0)-Boz(x) and applying the inhibit voltage VINH to theplurality of word lines Wz(0)-Wz(y) with the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) floatingso that voltages approximately equal to the inhibit voltage VINH areapplied to the top electrodes and the bottom electrodes of the resistivechange elements in the plurality of resistive change elements E00z-Oxyz. Floating a line refers to electrically connecting the line suchthat a voltage on the line exists due to a line capacitance of the line.The plurality of even bit lines Bez(0)-Bez(x) are floated bydisconnecting the plurality of even bit lines Bez(0)-Bez(x) from theplurality of global bit lines GB3(0)-GB3(x) by turning off the pluralityof even selection devices Nez0-Nezx in Section Z. The plurality of evenselection devices Nez0-Nezx are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELez having a low level. The plurality of odd bit lines Boz(0)-Boz(x)are floated by disconnecting the plurality of odd bit linesBoz(0)-Boz(x) from the plurality of global bit lines GB3(0)-GB3(x) byturning off the plurality of odd selection devices Noz0-Nozx in SectionZ. The plurality of odd selection devices Noz0-Nozx are turned off bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal SSELoz having a low level. It is noted that controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELez having a low level and a signal SSELoz havinga low level also turns off the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z. It is further noted that the reference line RL3floats because the first NMOS transistor 121 a and the second NMOStransistor 122 a of the reference line connection circuit 120 a forSection A are turned off and the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z are turned off.

The inhibit voltage VINH is applied to the plurality of word linesWz(0)-Wz(y) by the word line driver circuitry 110 z for Section Zdriving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110dz-11 ydz do not receive a voltage on the first power terminals becausethe first NMOS transistor 110 pz is turned off by control logic, such asa processor, a controller, and a microcontroller, supplying the signalS0 z having a low level and receive the inhibit voltage VINH on thesecond power terminals because the second NMOS transistor 111 pz isturned on by the control logic supplying the signal S1 z having a highlevel. The plurality of word line driver circuits 110 dz-11 ydz supplythe inhibit voltage VINH based on the plurality of signals ITE0 z-ITEyzsupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sz-11 ysz areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 z-SKyz have lowlevels.

Driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating causesvoltages on the plurality of word lines Wz(0)-Wz(y), voltages on theplurality of even bit lines Bez(0)-Bez(x), and voltages on the pluralityof odd bit lines Boz(0)-Boz(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bez(0)-Bez(x)and voltages on the plurality of odd bit lines Boz(0)-Boz(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wz(0)-Wz(y) through the plurality ofresistive change elements E00 z-Oxyz into the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x).The inhibit voltage VINH exists on the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) due toline capacitances because the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) are floating. Thus,driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 z-Oxyz.Additionally, driving voltages on the plurality of word linesWz(0)-Wz(y) to the inhibit voltage VINH with the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 z-Oxyz to be approximately 0volts.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states continues, as similarly discussedabove in step 304 of the flow chart 300, by biasing the plurality ofglobal bit lines GB3(0)-GB3(x). The plurality of global bit linesGB3(0)-GB3(x) are biased to the inhibit voltage VINH by floating theplurality of global bit lines GB3(0)-GB3(x) and applying the inhibitvoltage VINH to the plurality of global bit lines GB3(0)-GB3(x). Theplurality of global bit lines GB3(0)-GB3(x) are floated by disconnectingthe plurality of global bit lines GB3(0)-GB3(x) from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A, the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z, and the plurality of bus lines BL30-BL3 x. The plurality ofglobal bit lines GB3(0)-GB3(x) may be disconnected from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A as part of providing neutral voltageconditions for the plurality of resistive change elements E00 a-Oxya inSection A as discussed above. The plurality of global bit linesGB3(0)-GB3(x) may be disconnected from the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z as part of providing neutral voltage conditions for theplurality of resistive change elements E00 z-Oxyz in Section Z asdiscussed above. The plurality of global bit lines GB3(0)-GB3(x) aredisconnected from the plurality of bus lines BL30-BL3 x by turning offthe plurality of PMOS transistors 180 g-18 xg in the global bit lineconnection circuit 180. The plurality of PMOS transistors 180 g-18 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal CDO having a high level. Theinhibit voltage VINH is applied to the plurality of global bit linesGB3(0)-GB3(x) by electrically connecting the plurality of global bitlines GB3(0)-GB3(x) to a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH byturning on the plurality of NMOS transistors 130 k-13 xk in the keepercircuit 130. The plurality of NMOS transistors 130 k-13 xk are turned onby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states proceeds, as similarly discussed abovein step 306 of the flow chart 300, by selecting the odd resistive changeelements O01 a, Ox1 a in electrical communication with word line Wa(1)in Section A from the plurality of resistive change elements E00 a-Oxyain Section A and the plurality of resistive change elements E00 z-Oxyzin Section Z. The odd resistive change elements O01 a, Ox1 a inelectrical communication with word line Wa(1) in Section A are selectedfrom the plurality of resistive change elements E00 a-Oxya in Section Aand the plurality of resistive change elements E00 z-Oxyz in Section Zby control logic, such as a processor, a controller, and amicrocontroller. The resistive change elements E00 a-Ox0 a, EO1 a, Ex1a, and E0 ya-Oxya in the plurality of resistive change elements E00a-Oxya in Section A and the plurality of resistive change elements E00z-Oxyz in Section Z that are not selected are referred to as unselectedresistive change elements.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states continues, as similarly discussedabove in step 308 of the flow chart 300, by preparing the exemplary DDRcompatible implementation of the first exemplary architecture forapplying electrical stimuli to the odd resistive change elements O01,Ox1 a. The exemplary DDR compatible implementation of the firstexemplary architecture is prepared for applying electrical stimuli tothe odd resistive change elements O01, Ox1 a by changing electricalconnections of the plurality of odd bit lines Boa(0)-Boa(x), changingelectrical connections of the plurality of global bit linesGB3(0)-GB3(x), and disconnecting a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHfrom the plurality of global bit lines GB3(0)-GB3(x). The electricalconnections of the plurality of odd bit lines Boa(0)-Boa(x) and theelectrical connections of the plurality of global bit linesGB3(0)-GB3(x) are changed and a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH isdisconnected from the plurality of global bit lines GB3(0)-GB3(x) sothat voltages on the plurality of odd bit lines Boa(0)-Boa(x) can bedriven to voltages for applying electrical stimuli to the odd resistivechange elements O01 a, Ox1 a. The electrical connections of theplurality of odd bit lines Boa(0)-Boa(x) are changed so that theplurality of odd bit lines Boa(0)-Boa(x) are in electrical communicationwith the plurality of global bit lines GB3(0)-GB3(x). The plurality ofodd bit lines Boa(0)-Boa(x) are electrically connected to the pluralityof global bit lines GB3(0)-GB3(x) by turning on the plurality of oddselection devices Noa0-Noax. The plurality of odd selection devicesNoa0-Noax are turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELo having ahigh level. It is also noted that the control logic supplying a signalSSELo having a high level also turns on the second NMOS transistor 122 aof the reference line connection circuit 120 a for Section A and drivesthe voltage on the reference line RL3 to the inhibit voltage VINH byelectrically connecting the reference line RL3 through the second NMOStransistor 122 a of the reference line connection circuit 120 a and thesecond NMOS transistor 111 pa of the word line driver circuitry 110 a toa power supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH. It is further noted that, asdiscussed above with respect to providing neutral voltage conditions forthe plurality of resistive change elements E00 a-Oxya in Section A andthe plurality of resistive change elements E00 z-Oxyz in Section Z, thesecond NMOS transistor 111 pa of the word line driver circuitry 110 a isturned on.

The electrical connections of the plurality of global bit linesGB3(0)-GB3(x) are changed so that the plurality of global bit linesGB3(0)-GB3(x) are in electrical communication with the plurality of oddbit lines Boa(0)-Boa(x) and the plurality of bus lines BL30-BL3 x. Theplurality of global bit lines GB3(0)-GB3(x) are electrically connectedto the plurality of odd bit lines Boa(0)-Boa(x) by turning on theplurality of odd selection devices NoaO-Noax as discussed above. Theplurality of global bit lines GB3(0)-GB3(x) are electrically connectedto the plurality of bus lines BL30-BL3 x by turning on the plurality ofPMOS transistors 180 g-18 xg. The plurality of PMOS transistors 180 g-18xg are turned on by control logic, such as a processor, a controller,and a microcontroller, supplying a signal CDO having a low level. Apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the plurality ofglobal bit lines GB3(0)-GB3(x) by turning off the plurality of NMOStransistors 130 k-13 xk. The plurality of NMOS transistors 130 k-13 xkare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal KEEPe having a low level and asignal KEEPo having a low level.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states proceeds, as similarly discussed abovein step 310 of the flow chart 300, by applying electrical stimuli to theodd resistive change elements O01 a, Ox1 a to adjust resistive states ofthe odd resistive change elements O01 a, Ox1 a to low resistive states.Electrical stimuli to adjust resistive states of the odd resistivechange elements O01 a, Ox1 a to low resistive states cause current flowfrom the bottom electrodes BE of the odd resistive change elements O01a, Ox1 a to the top electrodes TE of the odd resistive change elementsO01 a, Ox1 a and the magnitudes of the voltages of the electricalstimuli are approximately equal to the system voltage VDD. As discussedabove, providing neutral voltage conditions for the plurality ofresistive change elements E00 a-Oxya in Section A causes voltages on theplurality of word lines Wa(0)-Wa(y), voltages on the plurality of evenbit lines Bea(0)-Bea(x), and voltages on the plurality of odd bit linesBoa(0)-Boa(x) to be approximately equal to the inhibit voltage VINH.Also, as discussed above, the plurality of global bit linesGB3(0)-GB3(x) are biased to the inhibit voltage VINH. Thus, electricalstimuli to adjust resistive states of the odd resistive change elementsO01 a, Ox1 a to low resistive states are applied to the odd resistivechange elements O01 a, Ox1 a by driving the voltage on the word lineWa(1) from approximately the inhibit voltage VINH to 0 volts or ground,driving the voltage on the global bit line GB3(0) and the voltage on theodd bit line Boa(0) from approximately the inhibit voltage VINH to thesystem voltage VDD, and driving the voltage on the global bit lineGB3(x) and the voltage on the odd bit line Boa(x) from approximately theinhibit voltage VINH to the system voltage VDD.

The voltage transition of the voltage on the word line Wa(1) generallycorresponds with the voltage transition of the voltage on the topelectrodes TE of the odd resistive change elements O01, Ox1 a becausethe voltage on the word line Wa(1) generally corresponds with thevoltage on the top electrodes TE of the odd resistive change elementsO01 a, Ox1 a. The voltage transition of the voltage on the odd bit lineBoa(0) generally corresponds with the voltage transition of the voltageon the bottom electrode BE of the resistive change element O01 a becausethe voltage on the odd bit line Boa(0) generally corresponds with thevoltage on the bottom electrode BE of the resistive change element O01a. The voltage transition of the voltage on the odd bit line Boa(x)generally corresponds with the voltage transition of the voltage on thebottom electrode BE of the resistive change element Ox1 a because thevoltage on the odd bit line Boa(x) generally corresponds with thevoltage on the bottom electrode BE of the resistive change element Ox1a. The magnitude of the voltage transitions for applying the electricalstimuli to the odd resistive change elements O01 a, Ox1 a to adjustresistive states of the odd resistive change elements O01 a, Ox1 a tolow resistive states are reduced because the voltage applied to the topelectrodes TE and the voltage applied to the bottom electrodes BE arenot required to transition by the magnitude of the system voltage VDD. Avoltage transition of 0 volts or ground minus the inhibit voltage VINHis required to place the top electrodes at 0 volts or ground and avoltage transition of the system voltage VDD minus the inhibit voltageVINH is required to place the bottom electrodes at the system voltageVDD. For example, when the inhibit voltage VINH is VDD/2 (half of thesystem voltage VDD), a voltage transition of 0 volts−VDD/2=−VDD/2 isrequired to place the top electrodes at 0 volts or ground and a voltagetransition of VDD−VDD/2=VDD/2 is required to place the bottom electrodesat the system voltage VDD. Further, the number of voltage transitionsfor applying the electrical stimulus to adjust resistive states of theodd resistive change elements OO1 a, Ox1 a to low resistive states isreduced because only voltages on the word line Wa(1), the global bitlines GB3(0)-GB3(x), and the odd bit lines Boa(0)-Boa(x) are adjustedfor applying electrical stimuli to adjust resistive states of the oddresistive change elements OO1 a, Ox1 a to low resistive states. It isnoted that applying the inhibit voltage VINH to a top electrode, abottom electrode, or both a top electrode and a bottom electrode of aresistive change element limits a voltage applied across a resistivechange element to a voltage less than a voltage limit for disturbing aresistive state of a resistive change element while applying electricalstimuli to the odd resistive change elements OO1 a, Ox1 a to adjustresistive states of the odd resistive change elements OO1 a, Ox1 a tolow resistive states.

The voltage on the word line Wa(1) is driven from the inhibit voltageVINH to 0 volts or ground by the word line driver circuit 111 da notsupplying a voltage and by electrically connecting the word line Wa(1)to a power supply, a voltage source, a driver circuit, or other devicethat supplies 0 volts or ground by turning on the sink transistor 111sa. The word line driver circuit 111 da does not supply a voltagebecause the word line driver circuit 111 da is set to supply a voltageon the first power terminal based on the signal ITE1 a supplied bycontrol logic, such as a processor, a controller, and a microcontroller,and the word line driver circuit 111 da does not receive a voltage onthe first power terminal because the first NMOS transistor 110 pa isturned off by the control logic suppling the signal S0 a having a lowlevel. The sink transistor 111 sa is turned on by control logic, such asa processor, a controller, and a microcontroller, supplying a signal SK1a having a high level. The voltages on the plurality of global bit linesGB3(0)-GB3(x) and the voltages on the plurality of odd bit linesBoa(0)-Boa(x) are driven from the inhibit voltage VINH to the systemvoltage VDD by the plurality of write buffer circuits 1500-150 xsupplying the system voltage VDD. The plurality of write buffer circuits1500-150 x supply the system voltage VDD based on the write set signalsWR00-WR0 x and the write reset signals WR10-WR1 x supplied by controllogic, such as a processor, a controller, and a microcontroller.

As shown in FIG. 1J-1, a current IO01 a flows through the resistivechange element O01 a from the bottom electrode BE to the top electrodeTE because the bottom electrode BE is at the system voltage VDD and thetop electrode TE is at 0 volts or ground. Also, as shown in FIG. 1J-1, acurrent IOx1 a flows through the resistive change element Ox1 a from thebottom electrode BE to the top electrode TE because the bottom electrodeBE is at the system voltage VDD and the top electrode TE is at 0 voltsor ground. FIG. 1J-1 also shows leakage currents flowing through theresistive change elements O00 a, O0 ya in electrical communication withthe odd bit line Boa(0), leakage currents flowing through the resistivechange elements Ox0 a, Oxya in electrical communication with the odd bitline Boa(x), and leakage currents flowing through the even resistivechange elements EO1 a, Ex1 a in electrical communication with the wordline Wa(1). The leakage currents are shown using dashed lines in FIG.1J-1. Leakage currents flow through the resistive change elements O00 a,O0 ya because the bottom electrodes of the resistive change elements O00a, O0 ya are at the system voltage VDD and the top electrodes of theresistive change elements O00 a, O0 ya are the inhibit voltage VINH.Leakage currents flow through the resistive change elements Ox0 a, Oxyabecause the bottom electrodes of the resistive change elements Ox0 a,Oxya are at the system voltage VDD and the top electrodes of theresistive change elements Ox0 a, Oxya are the inhibit voltage VINH.Leakage currents flow through the even resistive change elements E01 a,Ex1 a because the bottom electrodes of the even resistive changeelements E01 a, Ex1 a are at the inhibit voltage VINH and the topelectrodes of the even resistive change elements E01 a, Ex1 a are at 0volts or ground. It is noted that leakage currents may flow throughresistive change elements other than the resistive change elements inelectrical communication with the odd bit line Boa(0), the resistivechange elements in electrical communication with the odd bit lineBoa(x), and the resistive change elements in electrical communicationwith the word line Wa(1) because voltages on other lines may be impactedby applying electrical stimuli to adjust resistive states of the oddresistive change elements O01 a, Ox1 a to low resistive states. It isalso noted that leakage currents generally do not flow through theplurality of resistive change elements E00 z-Oxyz in Section Z becausethe bottom electrodes of the plurality of resistive change elements E00z-Oxyz are at the inhibit voltage VINH and the top electrodes of theplurality of resistive change elements E00 z-Oxyz are at the inhibitvoltage VINH. It is additionally noted that leakage currents do notprevent the PROGRAMMING operation of the odd resistive change elementsO01 a, Ox1 a when the leakage currents are much less than the amounts ofthe current IO01 a and the current IOx1 a. It is further noted that thevoltage differences across the resistive change elements that cause theleakage currents do not disturb the resistive states of the resistivechange elements because the voltage differences are less than a voltagelimit for disturbing a resistive state of a resistive change element.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states proceeds, as similarly discussed abovein step 312 of the flow chart 300, by restoring neutral voltageconditions for resistive change elements impacted by applying electricalstimuli to the odd resistive change elements O01 a, Ox1 a. Neutralvoltage conditions are restored for resistive change elements impactedby applying the electrical stimuli to the odd resistive change elementsO01 a, Ox1 a by floating the plurality of odd bit lines Boa(0)-Boa(x)and applying the inhibit voltage VINH to the word line Wa(1). Theplurality of even bit lines Bea(0)-Bea(x) are already floating becausethe plurality of even selection devices Nea0-Neax are turned off. Theinhibit voltage VINH is already applied to the word lines Wa(0), Wa(y)because the word line driver circuits 110 da, 11 yda are alreadysupplying the inhibit voltage VINH. The plurality of odd bit linesBoa(0)-Boa(x) are floated by disconnecting the plurality of odd bitlines Boa(0)-Boa(x) from the plurality of global bit lines GB3(0)-GB3(x)by turning off the plurality of odd selection devices Noa0-Noax. Theplurality of odd selection devices Noa0-Noax are turned off by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELo having a low level. The inhibit voltage VINH isapplied to the word line Wa(1) by turning off the sink transistor 111 saand by the word line driver circuit 111 da driving the voltage on theword line Wa(1) to the inhibit voltage VINH. The sink transistor 111 sais turned off by control logic, such as a processor, a controller, and amicrocontroller, supplying the signal SK1 a having a low level. The wordline driver circuit 111 da supplies the inhibit voltage VINH based onthe signal ITE1 a supplied by control logic, such as a processor, acontroller, and a microcontroller. Thus, the inhibit voltage VINH isapplied to the plurality of word lines Wa(0)-Wa(y) with the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) floating so that voltages approximately equal to theinhibit voltage VINH are applied to the top electrodes and the bottomelectrodes of the resistive change elements in the plurality ofresistive change elements E00 a-Oxya.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to low resistive states continues, as similarly discussedabove in step 314 of the flow chart 300, by biasing global bit linesimpacted by applying electrical stimuli to the odd resistive changeelement O01 a, Ox1 a. Global bit lines impacted by applying electricalstimuli to the odd resistive change elements O01 a, Ox1 a are biased tothe inhibit voltage VINH by floating the plurality of global bit linesGB3(0)-GB3(x) and applying the inhibit voltage VINH to the plurality ofglobal bit lines GB3(0)-GB3(x). The plurality of global bit linesGB3(0)-GB3(x) are floated by disconnecting the plurality of global bitlines GB3(0)-GB3(x) from the plurality of odd bit lines Boa(0)-Boa(x)and disconnecting the plurality of global bit lines GB3(0)-GB3(x) fromthe plurality of bus lines BL30-BL3 x. The plurality of global bit linesGB3(0)-GB3(x) are already disconnected from the plurality of even bitlines Bea(0)-Bea(x) because the plurality of even selection devicesNea0-Neax are turned off. The plurality of global bit linesGB3(0)-GB3(x) may be disconnected from the plurality of odd bit linesBoa(0)-Boa(x) as part of restoring neutral voltage conditions forresistive change elements impacted by applying the electrical stimuli tothe odd resistive change elements O01 a, Ox1 a as discussed above. Theplurality of global bit lines GB3(0)-GB3(x) are disconnected from theplurality of bus lines BL30-BL3 x by turning off the plurality of PMOStransistors 180 g-18 xg. The plurality of PMOS transistors 180 g-18 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal CDO having a high level. Theinhibit voltage VINH is applied to the plurality of global bit linesGB3(0)-GB3(x) by electrically connecting the plurality of global bitlines GB3(0)-GB3(x) to a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH byturning on the plurality of NMOS transistors 130 k-13 xk. The pluralityof NMOS transistors 130 k-13 xk are turned on by control logic, such asa processor, a controller, and a microcontroller, supplying a signalKEEPe having a high level and a signal KEEPo having a high level.

Referring now to FIGS. 1K-1, 1K-2, and 1K-3, a PROGRAMMING operation toadjust resistive states of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A to high resistive statesstarts, as similarly discussed above in step 302 of the flow chart 300,by providing neutral voltage conditions for the plurality of resistivechange elements E00 a-Oxya in Section A and the plurality of resistivechange elements E00 z-Oxyz in Section Z. The neutral voltage conditionsare provided for the plurality of resistive change elements E00 a-Oxyain section A by floating the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) and applying theinhibit voltage VINH to the plurality of word lines Wa(0)-Wa(y) with theplurality of even bit lines Bea(0)-Bea(x) and the plurality of odd bitlines Boa(0)-Boa(x) floating so that voltages approximately equal to theinhibit voltage VINH are applied to the top electrodes and the bottomelectrodes of the resistive change elements in the plurality ofresistive change elements E00 a-Oxya. Floating a line refers toelectrically connecting the line such that a voltage on the line existsdue to a line capacitance of the line. The plurality of even bit linesBea(0)-Bea(x) are floated by disconnecting the plurality of even bitlines Bea(0)-Bea(x) from the plurality of global bit lines GB3(0)-GB3(x)by turning off the plurality of even selection devices Nea0-Neax inSection A. The plurality of even selection devices Nea0-Neax are turnedoff by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELea having a low level. Theplurality of odd bit lines Boa(0)-Boa(x) are floated by disconnectingthe plurality of odd bit lines Boa(0)-Boa(x) from the plurality ofglobal bit lines GB3(0)-GB3(x) by turning off the plurality of oddselection devices Noa0-Noax in Section A. The plurality of odd selectiondevices Noa0-Noax are turned off by control logic, such as a processor,a controller, and a microcontroller, supplying a signal SSELoa having alow level. It is noted that control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELea having alow level and a signal SSELoa having a low level also turns off thefirst NMOS transistor 121 a and the second NMOS transistor 122 a of thereference line connection circuit 120 a for Section A.

The inhibit voltage VINH is applied to the plurality of word linesWa(0)-Wa(y) by the word line driver circuitry 110 a for Section Adriving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110da-11 yda receive the system voltage VDD on the first power terminalsbecause the first NMOS transistor 110 pa is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal S0 a having a high level and receive the inhibit voltage VINH onthe second power terminals because the second NMOS transistor 111 pa isturned on by the control logic supplying the signal S1 a having a highlevel. The plurality of word line driver circuits 110 da-11 yda supplythe inhibit voltage VINH based on the plurality of signals ITE0 a-ITEyasupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sa-11 ysa areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 a-SKya have lowlevels.

Driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating causesvoltages on the plurality of word lines Wa(0)-Wa(y), voltages on theplurality of even bit lines Bea(0)-Bea(x), and voltages on the pluralityof odd bit lines Boa(0)-Boa(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bea(0)-Bea(x)and voltages on the plurality of odd bit lines Boa(0)-Boa(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wa(0)-Wa(y) through the plurality ofresistive change elements E00 a-Oxya into the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x).The inhibit voltage VINH exists on the plurality of even bit linesBea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x) due toline capacitances because the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) are floating. Thus,driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 a-Oxya.Additionally, driving voltages on the plurality of word linesWa(0)-Wa(y) to the inhibit voltage VINH with the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 a-Oxya to be approximately 0volts.

The neutral voltage conditions are provided for the plurality ofresistive change elements E00 z-Oxyz in section Z by floating theplurality of even bit lines Bez(0)-Bez(x) and the plurality of odd bitlines Boz(0)-Boz(x) and applying the inhibit voltage VINH to theplurality of word lines Wz(0)-Wz(y) with the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) floatingso that voltages approximately equal to the inhibit voltage VINH areapplied to the top electrodes and the bottom electrodes of the resistivechange elements in the plurality of resistive change elements E00z-Oxyz. Floating a line refers to electrically connecting the line suchthat a voltage on the line exists due to a line capacitance of the line.The plurality of even bit lines Bez(0)-Bez(x) are floated bydisconnecting the plurality of even bit lines Bez(0)-Bez(x) from theplurality of global bit lines GB3(0)-GB3(x) by turning off the pluralityof even selection devices NezO-Nezx in Section Z. The plurality of evenselection devices NezO-Nezx are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELez having a low level. The plurality of odd bit lines Boz(0)-Boz(x)are floated by disconnecting the plurality of odd bit linesBoz(0)-Boz(x) from the plurality of global bit lines GB3(0)-GB3(x) byturning off the plurality of odd selection devices Noz0-Nozx in SectionZ. The plurality of odd selection devices Noz0-Nozx are turned off bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal SSELoz having a low level. It is noted that controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELez having a low level and a signal SSELoz havinga low level also turns off the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z. It is further noted that the reference line RL3floats because the first NMOS transistor 121 a and the second NMOStransistor 122 a of the reference line connection circuit 120 a forSection A are turned off and the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z are turned off.

The inhibit voltage VINH is applied to the plurality of word linesWz(0)-Wz(y) by the word line driver circuitry 110 z for Section Zdriving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110dz-11 ydz receive the system voltage VDD on the first power terminalsbecause the first NMOS transistor 110 pz is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal S0 z having a high level and receive the inhibit voltage VINH onthe second power terminals because the second NMOS transistor 111 pz isturned on by the control logic supplying the signal S1 z having a highlevel. The plurality of word line driver circuits 110 dz-11 ydz supplythe inhibit voltage VINH based on the plurality of signals ITE0 z-ITEyzsupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sz-11 ysz areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 z-SKyz have lowlevels.

Driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating causesvoltages on the plurality of word lines Wz(0)-Wz(y), voltages on theplurality of even bit lines Bez(0)-Bez(x), and voltages on the pluralityof odd bit lines Boz(0)-Boz(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bez(0)-Bez(x)and voltages on the plurality of odd bit lines Boz(0)-Boz(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wz(0)-Wz(y) through the plurality ofresistive change elements E00 z-Oxyz into the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x).The inhibit voltage VINH exists on the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) due toline capacitances because the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) are floating. Thus,driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 z-Oxyz.Additionally, driving voltages on the plurality of word linesWz(0)-Wz(y) to the inhibit voltage VINH with the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 z-Oxyz to be approximately 0volts.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to high resistive states continues, as similarly discussedabove in step 304 of the flow chart 300, by biasing the plurality ofglobal bit lines GB3(0)-GB3(x). The plurality of global bit linesGB3(0)-GB3(x) are biased to the inhibit voltage VINH by floating theplurality of global bit lines GB3(0)-GB3(x) and applying the inhibitvoltage VINH to the plurality of global bit lines GB3(0)-GB3(x). Theplurality of global bit lines GB3(0)-GB3(x) are floated by disconnectingthe plurality of global bit lines GB3(0)-GB3(x) from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A, the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z, and the plurality of bus lines BL30-BL3 x. The plurality ofglobal bit lines GB3(0)-GB3(x) may be disconnected from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A as part of providing neutral voltageconditions for the plurality of resistive change elements E00 a-Oxya inSection A as discussed above. The plurality of global bit linesGB3(0)-GB3(x) may be disconnected from the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z as part of providing neutral voltage conditions for theplurality of resistive change elements E00 z-Oxyz in Section Z asdiscussed above. The plurality of global bit lines GB3(0)-GB3(x) aredisconnected from the plurality of bus lines BL30-BL3 x by turning offthe plurality of PMOS transistors 180 g-18 xg in the global bit lineconnection circuit 180. The plurality of PMOS transistors 180 g-18 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal CDO having a high level. Theinhibit voltage VINH is applied to the plurality of global bit linesGB3(0)-GB3(x) by electrically connecting the plurality of global bitlines GB3(0)-GB3(x) to a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH byturning on the plurality of NMOS transistors 130 k-13 xk in the keepercircuit 130. The plurality of NMOS transistors 130 k-13 xk are turned onby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to high resistive states proceeds, as similarly discussedabove in step 306 of the flow chart 300, by selecting the odd resistivechange elements O01 a, Ox1 a in electrical communication with word lineWa(1) in Section A from the plurality of resistive change elements E00a-Oxya in Section A and the plurality of resistive change elements E00z-Oxyz in Section Z. The odd resistive change elements O01 a, Ox1 a inelectrical communication with word line Wa(1) in Section A are selectedfrom the plurality of resistive change elements E00 a-Oxya in Section Aand the plurality of resistive change elements E00 z-Oxyz in Section Zby control logic, such as a processor, a controller, and amicrocontroller. The resistive change elements E00 a-Ox0 a, EO1 a, Ex1a, and E0 ya-Oxya in the plurality of resistive change elements E00a-Oxya in Section A and the plurality of resistive change elements E00z-Oxyz in Section Z that are not selected are referred to as unselectedresistive change elements.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to high resistive states continues, as similarly discussedabove in step 308 of the flow chart 300, by preparing the exemplary DDRcompatible implementation of the first exemplary architecture forapplying electrical stimuli to the odd resistive change elements O01,Ox1 a. The exemplary DDR compatible implementation of the firstexemplary architecture is prepared for applying electrical stimuli tothe odd resistive change elements O01, Ox1 a by changing electricalconnections of the plurality of odd bit lines Boa(0)-Boa(x), changingelectrical connections of the plurality of global bit linesGB3(0)-GB3(x), and disconnecting a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHfrom the plurality of global bit lines GB3(0)-GB3(x). The electricalconnections of the plurality of odd bit lines Boa(0)-Boa(x) and theelectrical connections of the plurality of global bit linesGB3(0)-GB3(x) are changed and a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH isdisconnected from the plurality of global bit lines GB3(0)-GB3(x) sothat voltages on the plurality of odd bit lines Boa(0)-Boa(x) can bedriven to voltages for applying electrical stimuli to the odd resistivechange elements O01 a, Ox1 a. The electrical connections of theplurality of odd bit lines Boa(0)-Boa(x) are changed so that theplurality of odd bit lines Boa(0)-Boa(x) are in electrical communicationwith the plurality of global bit lines GB3(0)-GB3(x). The plurality ofodd bit lines Boa(0)-Boa(x) are electrically connected to the pluralityof global bit lines GB3(0)-GB3(x) by turning on the plurality of oddselection devices Noa0-Noax. The plurality of odd selection devicesNoa0-Noax are turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELo having ahigh level. It is also noted that the control logic supplying a signalSSELo having a high level also turns on the second NMOS transistor 122 aof the reference line connection circuit 120 a for Section A and drivesthe voltage on the reference line RL3 to the inhibit voltage VINH byelectrically connecting the reference line RL3 through the second NMOStransistor 122 a of the reference line connection circuit 120 a and thesecond NMOS transistor 111 pa of the word line driver circuitry 110 a toa power supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH. It is further noted that, asdiscussed above with respect to providing neutral voltage conditions forthe plurality of resistive change elements E00 a-Oxya in Section A andthe plurality of resistive change elements E00 z-Oxyz in Section Z, thesecond NMOS transistor 111 pa of the word line driver circuitry 110 a isturned on.

The electrical connections of the plurality of global bit linesGB3(0)-GB3(x) are changed so that the plurality of global bit linesGB3(0)-GB3(x) are in electrical communication with the plurality of oddbit lines Boa(0)-Boa(x) and the plurality of bus lines BL30-BL3 x. Theplurality of global bit lines GB3(0)-GB3(x) are electrically connectedto the plurality of odd bit lines Boa(0)-Boa(x) by turning on theplurality of odd selection devices Noa0-Noax as discussed above. Theplurality of global bit lines GB3(0)-GB3(x) are electrically connectedto the plurality of bus lines BL30-BL3 x by turning on the plurality ofPMOS transistors 180 g-18 xg. The plurality of PMOS transistors 180 g-18xg are turned on by control logic, such as a processor, a controller,and a microcontroller, supplying a signal CDO having a low level. Apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the plurality ofglobal bit lines GB3(0)-GB3(x) by turning off the plurality of NMOStransistors 130 k-13 xk. The plurality of NMOS transistors 130 k-13 xkare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal KEEPe having a low level and asignal KEEPo having a low level.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to high resistive states proceeds, as similarly discussedabove in step 310 of the flow chart 300, by applying electrical stimulito the odd resistive change elements O01 a, Ox1 a to adjust resistivestates of the odd resistive change elements O01 a, Ox1 a to highresistive states. Electrical stimuli to adjust resistive states of theodd resistive change elements O01 a, Ox1 a to high resistive statescause current flow from the top electrodes TE of the odd resistivechange elements O01 a, Ox1 a to the bottom electrodes BE of the oddresistive change elements O01 a, Ox1 a and the magnitudes of thevoltages of the electrical stimuli are approximately equal to the systemvoltage VDD. As discussed above, providing neutral voltage conditionsfor the plurality of resistive change elements E00 a-Oxya in Section Acauses voltages on the plurality of word lines Wa(0)-Wa(y), voltages onthe plurality of even bit lines Bea(0)-Bea(x), and voltages on theplurality of odd bit lines Boa(0)-Boa(x) to be approximately equal tothe inhibit voltage VINH. Also, as discussed above, the plurality ofglobal bit lines GB3(0)-GB3(x) are biased to the inhibit voltage VINH.Thus, electrical stimuli to adjust resistive states of the odd resistivechange elements O01 a, Ox1 a to high resistive states are applied to theodd resistive change elements O01 a, Ox1 a by driving the voltage on theword line Wa(1) from approximately the inhibit voltage VINH to thesystem voltage VDD, driving the voltage on the global bit line GB3(0)and the voltage on the odd bit line Boa(0) from approximately theinhibit voltage VINH to 0 volts or ground, and driving the voltage onthe global bit line GB3(x) and the voltage on the odd bit line Boa(x)from approximately the inhibit voltage VINH to 0 volts or ground.

The voltage transition of the voltage on the word line Wa(1) generallycorresponds with the voltage transition of the voltage on the topelectrodes TE of the odd resistive change elements O01, Ox1 a becausethe voltage on the word line Wa(1) generally corresponds with thevoltage on the top electrodes TE of the odd resistive change elementsO01 a, Ox1 a. The voltage transition of the voltage on the odd bit lineBoa(0) generally corresponds with the voltage transition of the voltageon the bottom electrode BE of the resistive change element O01 a becausethe voltage on the odd bit line Boa(0) generally corresponds with thevoltage on the bottom electrode BE of the resistive change element O01a. The voltage transition of the voltage on the odd bit line Boa(x)generally corresponds with the voltage transition of the voltage on thebottom electrode BE of the resistive change element Ox1 a because thevoltage on the odd bit line Boa(x) generally corresponds with thevoltage on the bottom electrode BE of the resistive change element Ox1a. The magnitude of the voltage transitions for applying the electricalstimuli to the odd resistive change elements O01 a, Ox1 a to adjustresistive states of the odd resistive change elements O01 a, Ox1 a tohigh resistive states are reduced because the voltage applied to the topelectrodes TE and the voltage applied to the bottom electrodes BE arenot required to transition by the magnitude of the system voltage VDD. Avoltage transition of the system voltage VDD minus the inhibit voltageVINH is required to place the top electrodes at the system voltage VDDand a voltage transition of 0 volts or ground minus the inhibit voltageVINH is required to place the bottom electrodes at 0 volts or ground.For example, when the inhibit voltage VINH is VDD/2 (half of the systemvoltage VDD), a voltage transition of VDD−VDD/2=VDD/2 is required toplace the top electrodes at the system voltage VDD and a voltagetransition of 0 volts−VDD/2=−VDD/2 is required to place the bottomelectrodes at 0 volts or ground. Further, the number of voltagetransitions for applying the electrical stimulus to adjust resistivestates of the odd resistive change elements OO1 a, Ox1 a to highresistive states is reduced because only voltages on the word lineWa(1), the global bit lines GB3(0)-GB3(x), and the odd bit linesBoa(0)-Boa(x) are adjusted for applying electrical stimuli to adjustresistive states of the odd resistive change elements OO1 a, Ox1 a tohigh resistive states. It is noted that applying the inhibit voltageVINH to a top electrode, a bottom electrode, or both a top electrode anda bottom electrode of a resistive change element limits a voltageapplied across a resistive change element to a voltage less than avoltage limit for disturbing a resistive state of a resistive changeelement while applying electrical stimuli to the odd resistive changeelements OO1 a, Ox1 a to adjust resistive states of the odd resistivechange elements OO1 a, Ox1 a to high resistive states.

The voltage on the word line Wa(1) is driven from the inhibit voltageVINH to the system voltage VDD by changing the voltage supplied by theword line driver circuit 111 da from the inhibit voltage VINH to thesystem voltage VDD. The word line driver circuit 111 da changes fromsupplying the inhibit voltage VINH to the system voltage VDD based on asignal ITE1 a supplied by control logic, such as a processor, acontroller, and a microcontroller. The voltages on the plurality ofglobal bit lines GB3(0)-GB3(x) and the voltages on the plurality of oddbit lines Boa(0)-Boa(x) are driven from the inhibit voltage VINH to 0volts or ground by the plurality of write buffer circuits 1500-150 xsupplying 0 volts or ground. The plurality of write buffer circuits1500-150 x supply 0 volts or ground based on the write set signalsWR00-WR0 x and the write reset signals WR10-WR1 x supplied by controllogic, such as a processor, a controller, and a microcontroller.

As shown in FIG. 1K-1, a current IO01 a flows through the resistivechange element O01 a from the top electrode TE to the bottom electrodeBE because the top electrode TE is at the system voltage VDD and thebottom electrode BE is at 0 volts or ground. Also, as shown in FIG.1K-1, a current IOx1 a flows through the resistive change element Ox1 afrom the top electrode TE to the bottom electrode BE because the topelectrode TE is at the system voltage VDD and the bottom electrode BE isat 0 volts or ground. FIG. 1K-1 also shows leakage currents flowingthrough the resistive change elements O00 a, O0 ya in electricalcommunication with the odd bit line Boa(0), leakage currents flowingthrough the resistive change elements Ox0 a, Oxya in electricalcommunication with the odd bit line Boa(x), and leakage currents flowingthrough the even resistive change elements E01 a, Ex1 a in electricalcommunication with the word line Wa(1). The leakage currents are shownusing dashed lines in FIG. 1K-1. Leakage currents flow through theresistive change elements O00 a, O0 ya because the top electrodes of theresistive change elements O00 a, O0 ya are at the inhibit voltage VINHand the bottom electrodes of the resistive change elements O00 a, O0 yaare at 0 volts or ground. Leakage currents flow through the resistivechange elements Ox0 a, Oxya because the top electrodes of the resistivechange elements Ox0 a, Oxya are at the inhibit voltage VINH and thebottom electrodes of the resistive change elements Ox0 a, Oxya are at 0volts or ground. Leakage currents flow through the even resistive changeelements E01 a, Ex1 a because the top electrodes of the even resistivechange elements EO1 a, Ex1 a are at the system voltage VDD and thebottom electrodes of the even resistive change elements EO1 a, Ex1 a areat the inhibit voltage VINH. It is noted that leakage currents may flowthrough resistive change elements other than the resistive changeelements in electrical communication with the odd bit line Boa(0), theresistive change elements in electrical communication with the odd bitline Boa(x), and the resistive change elements in electricalcommunication with the word line Wa(1) because voltages on other linesmay be impacted by applying electrical stimuli to adjust resistivestates of the odd resistive change elements O01 a, Ox1 a to highresistive states. It is also noted that leakage currents generally donot flow through the plurality of resistive change elements E00 z-Oxyzin Section Z because the bottom electrodes of the plurality of resistivechange elements E00 z-Oxyz are at the inhibit voltage VINH and the topelectrodes of the plurality of resistive change elements E00 z-Oxyz areat the inhibit voltage VINH. It is additionally noted that leakagecurrents do not prevent the PROGRAMMING operation of the odd resistivechange elements O01 a, Ox1 a when the leakage currents are much lessthan the amounts of the current IO01 a and the current IOx1 a. It isfurther noted that the voltage differences across the resistive changeelements that cause the leakage currents do not disturb the resistivestates of the resistive change elements because the voltage differencesare less than a voltage limit for disturbing a resistive state of aresistive change element.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to high resistive states proceeds, as similarly discussedabove in step 312 of the flow chart 300, by restoring neutral voltageconditions for resistive change elements impacted by applying electricalstimuli to the odd resistive change elements OO1 a, Ox1 a. Neutralvoltage conditions are restored for resistive change elements impactedby applying the electrical stimuli to the odd resistive change elementsOO1 a, Ox1 a by floating the plurality of odd bit lines Boa(0)-Boa(x)and applying the inhibit voltage VINH to the word line Wa(1). Theplurality of even bit lines Bea(0)-Bea(x) are already floating becausethe plurality of even selection devices Nea0-Neax are turned off. Theinhibit voltage VINH is already applied to the word lines Wa(0), Wa(y)because the word line driver circuits 110 da, 11 yda are alreadysupplying the inhibit voltage VINH. The plurality of odd bit linesBoa(0)-Boa(x) are floated by disconnecting the plurality of odd bitlines Boa(0)-Boa(x) from the plurality of global bit lines GB3(0)-GB3(x)by turning off the plurality of odd selection devices Noa0-Noax. Theplurality of odd selection devices Noa0-Noax are turned off by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELo having a low level. The inhibit voltage VINH isapplied to the word line Wa(1) by changing the voltage supplied by theword line driver circuit 111 da from the system voltage VDD to theinhibit voltage VINH. The word line driver circuit 111 da changes fromsupplying the system voltage VDD to the inhibit voltage VINH based on asignal ITE1 a supplied by control logic, such as a processor, acontroller, and a microcontroller. Thus, the inhibit voltage VINH isapplied to the plurality of word lines Wa(0)-Wa(y) with the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) floating so that voltages approximately equal to theinhibit voltage VINH are applied to the top electrodes and the bottomelectrodes of the resistive change elements in the plurality ofresistive change elements E00 a-Oxya.

The PROGRAMMING operation to adjust resistive states of odd resistivechange elements in electrical communication with word line Wa(1) inSection A to high resistive states continues, as similarly discussedabove in step 314 of the flow chart 300, by biasing global bit linesimpacted by applying electrical stimuli to the odd resistive changeelement O01 a, Ox1 a. Global bit lines impacted by applying electricalstimuli to the odd resistive change elements 001 a, Ox1 a are biased tothe inhibit voltage VINH by floating the plurality of global bit linesGB3(0)-GB3(x) and applying the inhibit voltage VINH to the plurality ofglobal bit lines GB3(0)-GB3(x). The plurality of global bit linesGB3(0)-GB3(x) are floated by disconnecting the plurality of global bitlines GB3(0)-GB3(x) from the plurality of odd bit lines Boa(0)-Boa(x)and disconnecting the plurality of global bit lines GB3(0)-GB3(x) fromthe plurality of bus lines BL30-BL3 x. The plurality of global bit linesGB3(0)-GB3(x) are already disconnected from the plurality of even bitlines Bea(0)-Bea(x) because the plurality of even selection devicesNea0-Neax are turned off. The plurality of global bit linesGB3(0)-GB3(x) may be disconnected from the plurality of odd bit linesBoa(0)-Boa(x) as part of restoring neutral voltage conditions forresistive change elements impacted by applying the electrical stimuli tothe odd resistive change elements O01 a, Ox1 a as discussed above. Theplurality of global bit lines GB3(0)-GB3(x) are disconnected from theplurality of bus lines BL30-BL3 x by turning off the plurality of PMOStransistors 180 g-18 xg. The plurality of PMOS transistors 180 g-18 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal CDO having a high level. Theinhibit voltage VINH is applied to the plurality of global bit linesGB3(0)-GB3(x) by electrically connecting the plurality of global bitlines GB3(0)-GB3(x) to a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH byturning on the plurality of NMOS transistors 130 k-13 xk. The pluralityof NMOS transistors 130 k-13 xk are turned on by control logic, such asa processor, a controller, and a microcontroller, supplying a signalKEEPe having a high level and a signal KEEPo having a high level.

Referring now to FIGS. 1L-1, 1L-2, and 1L-3, a READ operation of oddresistive change elements in electrical communication with word lineWa(1) starts, as similarly discussed above in step 402 of the flow chart400, by providing neutral voltage conditions for the plurality ofresistive change elements E00 a-Oxya in Section A and the plurality ofresistive change elements E00 z-Oxyz in Section Z. The neutral voltageconditions are provided for the plurality of resistive change elementsE00 a-Oxya in section A by floating the plurality of even bit linesBea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x) andapplying the inhibit voltage VINH to the plurality of word linesWa(0)-Wa(y) with the plurality of even bit lines Bea(0)-Bea(x) and theplurality of odd bit lines Boa(0)-Boa(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00 a-Oxya. Floating a linerefers to electrically connecting the line such that a voltage on theline exists due to a line capacitance of the line. The plurality of evenbit lines Bea(0)-Bea(x) are floated by disconnecting the plurality ofeven bit lines Bea(0)-Bea(x) from the plurality of global bit linesGB3(0)-GB3(x) by turning off the plurality of even selection devicesNea0-Neax in Section A. The plurality of even selection devicesNea0-Neax are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELea having alow level. The plurality of odd bit lines Boa(0)-Boa(x) are floated bydisconnecting the plurality of odd bit lines Boa(0)-Boa(x) from theplurality of global bit lines GB3(0)-GB3(x) by turning off the pluralityof odd selection devices NoaO-Noax in Section A. The plurality of oddselection devices NoaO-Noax are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELoa having a low level. It is noted that control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELea having a low level and a signal SSELoa having a low level alsoturns off the first NMOS transistor 121 a and the second NMOS transistor122 a of the reference line connection circuit 120 a for Section A.

The inhibit voltage VINH is applied to the plurality of word linesWa(0)-Wa(y) by the word line driver circuitry 110 a for Section Adriving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110da-11 yda receive the system voltage VDD on the first power terminalsbecause the first NMOS transistor 110 pa is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal S0 a having a high level and receive the inhibit voltage VINH onthe second power terminals because the second NMOS transistor 111 pa isturned on by the control logic supplying the signal S1 a having a highlevel. The plurality of word line driver circuits 110 da-11 yda supplythe inhibit voltage VINH based on the plurality of signals ITE0 a-ITEyasupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sa-11 ysa areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 a-SKya have lowlevels.

Driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating causesvoltages on the plurality of word lines Wa(0)-Wa(y), voltages on theplurality of even bit lines Bea(0)-Bea(x), and voltages on the pluralityof odd bit lines Boa(0)-Boa(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bea(0)-Bea(x)and voltages on the plurality of odd bit lines Boa(0)-Boa(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wa(0)-Wa(y) through the plurality ofresistive change elements E00 a-Oxya into the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x).The inhibit voltage VINH exists on the plurality of even bit linesBea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x) due toline capacitances because the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) are floating. Thus,driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 a-Oxya.Additionally, driving voltages on the plurality of word linesWa(0)-Wa(y) to the inhibit voltage VINH with the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 a-Oxya to be approximately 0volts.

The neutral voltage conditions are provided for the plurality ofresistive change elements E00 z-Oxyz in section Z by floating theplurality of even bit lines Bez(0)-Bez(x) and the plurality of odd bitlines Boz(0)-Boz(x) and applying the inhibit voltage VINH to theplurality of word lines Wz(0)-Wz(y) with the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) floatingso that voltages approximately equal to the inhibit voltage VINH areapplied to the top electrodes and the bottom electrodes of the resistivechange elements in the plurality of resistive change elements E00z-Oxyz. Floating a line refers to electrically connecting the line suchthat a voltage on the line exists due to a line capacitance of the line.The plurality of even bit lines Bez(0)-Bez(x) are floated bydisconnecting the plurality of even bit lines Bez(0)-Bez(x) from theplurality of global bit lines GB3(0)-GB3(x) by turning off the pluralityof even selection devices Nez0-Nezx in Section Z. The plurality of evenselection devices Nez0-Nezx are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELez having a low level. The plurality of odd bit lines Boz(0)-Boz(x)are floated by disconnecting the plurality of odd bit linesBoz(0)-Boz(x) from the plurality of global bit lines GB3(0)-GB3(x) byturning off the plurality of odd selection devices Noz0-Nozx in SectionZ. The plurality of odd selection devices Noz0-Nozx are turned off bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal SSELoz having a low level. It is noted that controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELez having a low level and a signal SSELoz havinga low level also turns off the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z. It is further noted that the reference line RL3floats because the first NMOS transistor 121 a and the second NMOStransistor 122 a of the reference line connection circuit 120 a forSection A are turned off and the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z are turned off.

The inhibit voltage VINH is applied to the plurality of word linesWz(0)-Wz(y) by the word line driver circuitry 110 z for Section Zdriving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110dz-11 ydz receive the system voltage VDD on the first power terminalsbecause the first NMOS transistor 110 pz is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal S0 z having a high level and receive the inhibit voltage VINH onthe second power terminals because the second NMOS transistor 111 pz isturned on by the control logic supplying the signal S1 z having a highlevel. The plurality of word line driver circuits 110 dz-11 ydz supplythe inhibit voltage VINH based on the plurality of signals ITE0 z-ITEyzsupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sz-11 ysz areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 z-SKyz have lowlevels.

Driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating causesvoltages on the plurality of word lines Wz(0)-Wz(y), voltages on theplurality of even bit lines Bez(0)-Bez(x), and voltages on the pluralityof odd bit lines Boz(0)-Boz(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bez(0)-Bez(x)and voltages on the plurality of odd bit lines Boz(0)-Boz(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wz(0)-Wz(y) through the plurality ofresistive change elements E00 z-Oxyz into the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x).The inhibit voltage VINH exists on the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) due toline capacitances because the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) are floating. Thus,driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 z-Oxyz.Additionally, driving voltages on the plurality of word linesWz(0)-Wz(y) to the inhibit voltage VINH with the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 z-Oxyz to be approximately 0volts.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 404 of the flow chart 400, by biasing theplurality of global bit lines GB3(0)-GB3(x). The plurality of global bitlines GB3(0)-GB3(x) are biased to the inhibit voltage VINH by floatingthe plurality of global bit lines GB3(0)-GB3(x) and applying the inhibitvoltage VINH to the plurality of global bit lines GB3(0)-GB3(x). Theplurality of global bit lines GB3(0)-GB3(x) are floated by disconnectingthe plurality of global bit lines GB3(0)-GB3(x) from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A, the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z, and the plurality of bus lines BL30-BL3 x. The plurality ofglobal bit lines GB3(0)-GB3(x) may be disconnected from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A as part of providing neutral voltageconditions for the plurality of resistive change elements E00 a-Oxya inSection A as discussed above. The plurality of global bit linesGB3(0)-GB3(x) may be disconnected from the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z as part of providing neutral voltage conditions for theplurality of resistive change elements E00 z-Oxyz in Section Z asdiscussed above. The plurality of global bit lines GB3(0)-GB3(x) aredisconnected from the plurality of bus lines BL30-BL3 x by turning offthe plurality of PMOS transistors 140 g-14 xg in the global bit lineconnection circuit 140. The plurality of PMOS transistors 140 g-14 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a plurality of signals YD0-YDx having highlevels. The inhibit voltage VINH is applied to the plurality of globalbit lines GB3(0)-GB3(x) by electrically connecting the plurality ofglobal bit lines GB3(0)-GB3(x) to a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHby turning on the plurality of NMOS transistors 130 k-13 xk in thekeeper circuit 130. The plurality of NMOS transistors 130 k-13 xk areturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A proceeds, as similarlydiscussed above in step 406 of the flow chart 400, by selecting the oddresistive change elements O01 a, Ox1 a in electrical communication withword line Wa(1) in Section A from the plurality of resistive changeelements E00 a-Oxya in Section A and the plurality of resistive changeelements E00 z-Oxyz in Section Z. The odd resistive change elements O01a, Ox1 a in electrical communication with word line Wa(1) in Section Aare selected from the plurality of resistive change elements E00 a-Oxyain Section A and the plurality of resistive change elements E00 z-Oxyzin Section Z by control logic, such as a processor, a controller, and amicrocontroller. The resistive change elements E00 a-Ox0 a, E01 a, Ex1a, and E0 ya-Oxya in the plurality of resistive change elements E00a-Oxya in Section A and the plurality of resistive change elements E00z-Oxyz in Section Z that are not selected are referred to as unselectedresistive change elements.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 408 of the flow chart 400, by preparing theexemplary DDR compatible implementation of the first exemplaryarchitecture for determining resistive states of the odd resistivechange elements O01 a, Ox1 a. The exemplary DDR compatibleimplementation of the first exemplary architecture is prepared fordetermining resistive states of the odd resistive change elements O01 a,Ox1 a by driving the voltage on the reference line RL3 to the inhibitvoltage VINH, changing electrical connections of the plurality of oddbit lines Boa(0)-Boa(x), changing electrical connections of theplurality of global bit lines GB3(0)-GB3(0), and disconnecting a powersupply, a voltage source, a driver circuit, or the device that suppliesthe inhibit voltage VINH from the plurality of global bit linesGB3(0)-GB3(x). The voltage on the reference line RL3 is driven to theinhibit voltage VINH by electrically connecting the reference line RL3through the second NMOS transistor 122 a of the reference lineconnection circuit 120 a and the second NMOS transistor 111 pa of theword line driver circuit 110 a to a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINH.The second NMOS transistor 122 a is turned on by control logic, such asa processor, a controller, and a microcontroller, supplying a signalSSELoa having a high level and, as discussed above with respect toproviding neutral voltage conditions for the plurality of resistivechange elements E00 a-Oxya in Section A and the plurality of resistivechange elements E00 z-Oxyz in Section Z, the second NMOS transistor 111pa of the word line driver circuit 110 a is turned on.

The electrical connections of the plurality of odd bit linesBoa(0)-Boa(x) and the electrical connections of the plurality of globalbit lines GB3(0)-GB3(x) are changed and a power supply, a voltagesource, a driver circuit, or other device that supplies the inhibitvoltage VINH is disconnected from the plurality of global bit linesGB3(0)-GB3(x) so that voltages indicative of the resistive states of theodd resistive change elements O01 a, Ox1 a can be generated on theplurality of odd bit lines Boa(0)-Boa(x), the plurality of global bitlines GB3(0)-GB3(x), and the plurality of bus lines BL30-BL3 x. Theelectrical connections of the plurality of odd bit lines Boa(0)-Boa(x)are changed so that the plurality of odd bit lines Boa(0)-Boa(x) are inelectrical communication with the plurality of global bit linesGB3(0)-GB3(x). The plurality of odd bit lines Boa(0)-Boa(x) areelectrically connected to the plurality of global bit linesGB3(0)-GB3(x) by turning on the plurality of odd selection devicesNoa0-Noax. The plurality of odd selection devices Noa0-Noax are turnedon by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a high level. Theplurality of odd bit lines Boa(0)-Boa(x) may be electrically connectedto the plurality of global bit lines GB3(0)-GB3(x) as part of drivingthe voltage on the reference line RL3 to the inhibit voltage VINH asdiscussed above.

The electrical connections of the plurality of global bit linesGB3(0)-GB3(x) are changed so that the plurality of global bit linesGB3(0)-GB3(x) are in electrical communication with the plurality of oddbit lines Boa(0)-Boa(x) and the plurality of bus lines BL30-BL3 x. Theplurality of global bit lines GB3(0)-GB3(x) are electrically connectedto the plurality of odd bit lines Boa(0)-Boa(x) by turning on theplurality of odd selection devices Noa0-Noax as discussed above and theplurality of global bit lines GB3(0)-GB3(x) may be electricallyconnected to the plurality of odd bit lines Boa(0)-Boa(x) as part ofdriving the voltage on the reference line RL3 to the inhibit voltageVINH as discussed above. The plurality of global bit lines GB3(0)-GB3(x)are electrically connected to the plurality of bus lines BL30-BL3 x byturning on the plurality of PMOS transistors 180 g-180 x. The pluralityof PMOS transistors 180 g-180 x are turned on by control logic, such asa processor, a controller, and a microcontroller, supplying a signal CD0having a low level. A power supply, a voltage source, a driver circuit,or other device that supplies the inhibit voltage VINH is disconnectedfrom the plurality of global bit lines GB3(0)-GB3(x) by turning off theplurality of NMOS transistors 130 k-13 xk. The plurality of NMOStransistors 130 k-13 xk are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signal KEEPehaving a low level and a signal KEEPo having a low level.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 410 of the flow chart 400, by generatingvoltages indicative of resistive states of the odd resistive changeelements O01 a, Ox1 a. Voltages indicative of resistive states of theodd resistive change elements O01 a, Ox1 a are generated on theplurality of odd bit lines Boa(0)-Boa(x), the plurality of global bitlines GB3(0)-GB3(x), and the plurality of bus lines BL30-BL3 x bydriving the voltage on the word line Wa(1) to the system voltage VDD andsinking an amount of current for a READ operation from each bus line ofthe plurality of bus lines BL30-BL3 x. As discussed above, providingneutral voltage conditions for the plurality of resistive changeelements E00 a-Oxya causes voltages on the plurality of word linesWa(0)-Wa(y), voltages on the plurality of even bit lines Bea(0)-Bea(x),and voltages on the plurality of odd bit lines Boa(0)-Boa(x) to beapproximately equal to the inhibit voltage VINH. Also, as discussedabove, the plurality of global bit lines GB3(0)-GB3(x) are biased to theinhibit voltage VINH. Thus, for generating voltages indicative ofresistive states of the odd resistive change elements O01 a, Ox1 a, avoltage on the word line Wa(1) transitions from the inhibit voltage VINHto the system voltage VDD and the voltages on the plurality of odd bitlines Boa(0)-Boa(x) and the plurality of global bit lines GB3(0)-GB3(x)transition from the inhibit voltage VINH to voltages indicative ofresistive states of the odd resistive change elements O01 a, Ox1 a.

The voltage transition of the voltage on the word line Wa(1) generallycorresponds with the voltage transition of the voltage on the topelectrodes TE of the odd resistive change elements O01 a, Ox1 a becausethe voltage on the word line Wa(1) generally corresponds with thevoltage on the top electrodes TE of the odd resistive change elementsO01 a, Ox1 a. The voltage transitions of the voltages on the pluralityof odd bit lines Boa(0)-Boa(x) generally corresponds with the voltagetransitions of the voltages on the bottom electrodes BE of the oddresistive change elements OO1 a, Ox1 a because the voltages on theplurality of odd bit lines Boa(0)-Boa(x) generally corresponds with thevoltages on the bottom electrodes BE of the odd resistive changeelements OO1 a, Ox1 a. The magnitude of the voltage transition to placethe top electrodes TE of the odd resistive change elements OO1 a, Ox1 aat the system voltage VDD for generating voltages indicative ofresistive states of the odd resistive change elements OO1 a, Ox1 a isreduced because the voltage applied to the top electrodes TE of the oddresistive change elements OO1 a, Ox1 a is not required to transition bythe magnitude of the system voltage VDD. A voltage transition of thesystem voltage VDD minus the inhibit voltage VINH is required to placethe top electrodes at the system voltage VDD. For example, when theinhibit voltage VINH is VDD/2 (half of the system voltage VDD) a voltagetransition of VDD−VDD/2=VDD/2 is required to place the top electrodes atthe system voltage VDD. Further, the number of voltage transitions forgenerating voltages indicative of resistive states of the odd resistivechange elements OO1 a, Ox1 a is reduced because only voltages on theword line Wa(1), the plurality of global bit lines GB3(0)-GB(x), and theplurality of odd bit lines Boa(0)-Boa(x) are adjusted for generatingvoltages indicative of resistive states of the odd resistive changeelements OO1 a, Ox1 a. It is noted that applying the inhibit voltageVINH to a top electrode, a bottom electrode, or both a top electrode anda bottom electrode of a resistive change element limits a voltageapplied across a resistive change element to a voltage less than avoltage limit for disturbing a resistive state of a resistive changeelement while generating voltages indicative of resistive states of theodd resistive change elements O01 a, Ox1 a.

The voltage on the word line Wa(1) is driven from the inhibit voltageVINH to the system voltage VDD by changing the voltage supplied by theword line driver circuit 111 da from the inhibit voltage VINH to thesystem voltage VDD. The word line driver circuit 111 da changes fromsupplying the inhibit voltage VINH to the system voltage VDD based on asignal ITE1 a supplied by control logic, such as a processor, acontroller, and a microcontroller. The plurality of write buffercircuits 1500-150 x do not supply voltages based on the write setsignals WR00-WR0 x and the write reset signals WR10-WR1 x supplied bycontrol logic, such as a processor, a controller, and a microcontroller.The amount of current for a READ operation is sunk from each bus line ofthe plurality of bus lines BL30-BL3 x by the current source inelectrical communication with that bus line. The amount of current for aREAD operation is based on the amount of current that would flow througha resistor having an intermediate resistance and having the systemvoltage VDD applied to one terminal of the resistor and the inhibitvoltage VINH applied to the other terminal of the resistor. The amountof current that would flow through a resistor having an intermediateresistance and having the system voltage VDD applied to one terminal ofthe resistor and the inhibit voltage VINH applied to the other terminalof the resistor can be approximated by the following equation,I=(VDD−VINH)/Intermediate Resistance. For example, when the intermediateresistance=5.5MΩ, the system voltage VDD=2V, and the inhibit voltageVINH=1V, each current source of the plurality of current sources1600-160 x is configured to sink an amount of current that can beapproximated as I=(2V−1V)/5.5MΩ=0.18 μA. It is noted that, ignoringleakage currents, the amount of current for the READ operation flowsthrough each odd resistive change element O01 a,Ox1 a in electricalcommunication with the word line Wa(1), each odd bit line of theplurality of odd bit lines Boa(0)-Boa(x), each global bit line of theplurality of global bit lines GB3(0)-GB3(x), and each bus line of theplurality of bus lines BL30-BL3 x to each current source of theplurality of current sources 1600-160 x.

The intermediate resistance sets a boundary for resistance values thatcorrespond with a low resistive state during READ operations andresistance values that correspond with a high resistive state duringREAD operations. The intermediate resistance is a design variable thatcan be selected by a circuit designer and the circuit designer typicallyselects an intermediate resistance greater than a model resistance for alow resistive state of a resistive change element and less than a modelresistance for a high resistive state of a resistive change element. Forexample, when a model resistance for a low resistive state of aresistive change element is 1MΩ and a model resistance for a highresistive state of a resistive change elements is 10MΩ, a circuitdesigner can select an intermediate resistance of 5.5MΩ so thatresistive change elements having a resistance less than approximately5.5MΩ are determined to have a low resistive state during READoperations and resistive change elements having a resistance greaterthan approximately 5.5MΩ are determined to have a high resistive stateduring READ operations. It is noted that the intermediate resistance isnot limited to a resistance at the exact midpoint between a modelresistance for a low resistive state of a resistive change element and amodel resistance for a high resistive state of a resistive changeelement, but rather the intermediate resistance can be closer the modelresistance for the low resistive state or the model resistance for thehigh resistive state.

FIG. 1L-1 shows a current IO01 a flowing through the resistive changeelement OO1 a from the top electrode TE to the bottom electrode BEbecause the top electrode TE is at the system voltage VDD and the bottomelectrode BE is at a voltage indicative of a resistive state of theresistive change element OO1 a. FIG. 1L-1 also shows a current IOx1 aflowing through the resistive change element Ox1 a from the topelectrode TE to the bottom electrode BE because the top electrode TE isat the system voltage VDD and the bottom electrode BE is at a voltageindicative of a resistive state of the resistive change element Ox1 a.While, ignoring leakage currents, the amount of the current flowingthrough the resistive change element OO1 a, the odd bit line Boa(0), theglobal bit line GB3(0), and the bus line BL30 are the same amount ofcurrent (the amount of current for the READ operation) and the amount ofthe current flowing through the resistive change element Ox1 a, the oddbit line Boa(x), the global bit line GB3(x), and the bus line BL3 x arethe same amount of current (the amount of current for the READoperation). Additionally, ignoring leakage currents, routing parasitics,and an on resistance of an odd selection device of the plurality of oddselection devices NoaO-Noax, the voltage on an odd bit line in theplurality of odd bit lines Boa(0)-Boa(x), the voltage on a global bitline in the plurality of global bit lines GB3(0)-GB3(x), and the voltageon a bus line in the plurality of bus lines BL30-BL3 x having the samecolumn number are generally the same voltage and the voltage on an oddbit line in the plurality of odd bit lines Boa(0)-Boa(x), the voltage ona global bit line in the plurality of global bit lines GB3(0)-GB3(x),and the voltage on a bus line in the plurality of bus lines BL30-BL3 xhaving the same column number are indicative of a resistive state of anodd resistive change element in the odd resistive change elements OO1 a,Ox1 a having the same column number. It is noted that the voltageindicative of a resistive state of the resistive change element OO1 a isdiscussed below with respect to the voltage VGB3(0) on the global bitline GB3(0) and the voltage indicative of a resistive state of theresistive change element Ox1 a is discussed below with respect to thevoltage VGB3(x) on the global bit line GB3(x).

The voltage VGB3(0) on the global bit line GB3(0), ignoring leakagecurrents, routing parasitics, and on resistance of the odd selectiondevice NoaO, can be approximated by subtracting the voltage drop acrossthe resistive change element O01 a from the voltage VWa(1) on the wordline Wa(1). The voltage drop across the resistive change element OO1 acan be approximated using Ohm's Law. Thus, the voltage VGB3(0) on theglobal bit line GB3(0) can be approximated by the following equationVGB3(0)=VWa(1)−(IO01 a×RO01 a), where VWa(1) is the voltage on the wordline Wa(1), the current IO01 a is the current flowing through resistivechange element OO1 a, and RO01 a is the resistance of the resistivechange element OO1 a. As shown by this equation, the voltage VGB3(0) onthe global bit line GB3(0) changes when the resistance of the resistivechange element OO1 a changes because the voltage VWa(1) on the word lineWa(1) and the current IO01 a flowing through the resistive changeelement OO1 a are generally the same for READ operations. For example,when VWa(1)=2 volts, IO01 a=1/5.5 microamps, and RO01 a=5.5MΩ, thevoltage VGB3(0)=2V−(1/5.5 μA×5.5MΩ)=1V. For example, when VWa(1)=2volts, IO01 a=1/5.5 microamps, and RO01 a=1MΩ, the voltageVGB3(0)=2V−(1/5.5 μA×1MΩ)=1.82V. For example, when VWa(1)=2 volts, IO01a=1/5.5 microamps, and RO01 a=10MΩ, the voltage VGB3(0)=2V−(1/5.5 ∥A×10MΩ)=0.182V.

The voltage VGB3(x) on the global bit line GB3(x), ignoring leakagecurrents, routing parasitics, and on resistance of the odd selectiondevice Noax, can be approximated by subtracting the voltage drop acrossthe resistive change element Ox1 a from the voltage VWa(1) on the wordline Wa(1). The voltage drop across the resistive change element Ox1 acan be approximated using Ohm's Law. Thus, the voltage VGB3(x) on theglobal bit line GB3(x) can be approximated by the following equationVGB3(x)=VWa(1)−(IOx1 a×ROx1 a), where VWa(1) is the voltage on the wordline Wa(1), the current IOx1 a is the current flowing through resistivechange element Ox1 a, and ROx1 a is the resistance of the resistivechange element Ox1 a. As shown by this equation, the voltage VGB3(x) onthe global bit line GB3(x) changes when the resistance of the resistivechange element Ox1 a changes because the voltage VWa(1) on the word lineWa(1) and the current IOx1 a flowing through the resistive changeelement Ox1 a are generally the same for READ operations. For example,when VWa(1)=2 volts, IOx1 a=1/5.5 microamps, and ROx1 a=5.5MΩ, thevoltage VGB3(x)=2V−(1/5.5 μA×5.5MΩ)=1V. For example, when VWa(1)=2volts, IOx1 a=1/5.5 microamps, and ROx1 a=1MΩ, the voltageVGB3(x)=2V−(1/5.5 μA×1MΩ)=1.82V. For example, when VWa(1)=2 volts, IOx1a=1/5.5 microamps, and ROx1 a=10MΩ, the voltage VGB3(x)=2V−(1/5.5 μA×10MΩ)=0.182V.

FIG. 1L-1 also shows leakage currents flowing through the resistivechange elements O00 a, O0 ya in electrical communication with the oddbit line Boa(0), leakage currents flowing through the resistive changeelements Ox0 a, Oxya in electrical communication with the odd bit lineBoa(x), and leakage currents flowing through the resistive changeelements E01 a, Ex1 a in electrical communication with the word lineWa(1). The leakage currents are shown using dashed lines in FIG. 1L-1.Leakage currents flow through the resistive change elements O00 a, O0 yabecause the bottom electrodes of the resistive change elements O00 a, O0ya are at a voltage indicative of a resistive state of the resistivechange element OO1 a and the top electrodes of the resistive changeelements O00 a, O0 ya are the inhibit voltage VINH. Leakage currentsflow through the resistive change elements Ox0 a, Oxya because thebottom electrodes of the resistive change elements Ox0 a, Oxya are at avoltage indicative of a resistive state of the resistive change elementOx1 a and the top electrodes of the resistive change elements Ox0 a,Oxya are the inhibit voltage VINH. Leakage currents flow throughresistive change elements E01 a, Ex1 a because the bottom electrodes ofthe resistive change elements E01 a, Ex1 a are at the inhibit voltageVINH and the top electrodes of the resistive change elements E01 a, Ex1a are at the system voltage VDD. It is noted that leakage currents mayflow through resistive change elements other than the resistive changeelements in electrical communication with the odd bit line Boa(0), theresistive change elements in electrical communication with the odd bitline Boa(x), and the resistive change elements in electricalcommunication with the word line Wa(1) because voltages on other linesmay be impacted by generating voltages indicative of resistive states ofthe odd resistive change elements OO1 a, Ox1 a. It is also noted thatleakage currents generally do not flow through the plurality ofresistive change elements E00 z-Oxyz in Section Z because the bottomelectrodes of the plurality of resistive change elements E00 z-Oxyz areat the inhibit voltage VINH and the top electrodes of the plurality ofresistive change elements E00 z-Oxyz are at the inhibit voltage VINH. Itis additionally noted that leakage currents do not prevent the READoperation of the odd resistive change elements O01 a, Ox1 a when theleakage currents are much less than the amounts of the current IO01 aand the current IOx1 a. It is further noted that the voltage differencesacross the resistive change elements that cause the leakage currents donot disturb the resistive states of the resistive change elementsbecause the voltage differences are less than a voltage limit fordisturbing a resistive state of a resistive change element.

FIG. 1L-1 shows leakage currents flowing through the resistive changeelements O00 a, O0 ya from the odd bit line Boa(0) because the resistivechange element O01 a has a low resistive state and a voltage indicativeof a low resistive state of resistive change element O01 a is greaterthan the inhibit voltage VINH. FIG. 1L-1 shows leakage currents flowingthrough the resistive change elements Ox0 a, Oxya into the odd bit lineBoa(x) because the resistive change element Ox1 a has a high resistivestate and a voltage indicative of a high resistive state of resistivechange element Ox1 a is greater than the inhibit voltage VINH. It isnoted that when the voltage VBoa(0) on the odd bit line Boa(0) is lessthan the inhibit voltage VINH and the word lines Wa(0), Wa(y) inelectrical communication with the other resistive change elements O00 a,O0 ya on the odd bit line Boa(0) are driven to the inhibit voltage VINH,leakage currents flow into the odd bit line Boa(0) through the otherresistive change elements O00 a, O0 ya and pull up the voltage VBoa(0)on the odd bit line Boa(0). It is also noted that when the voltageVBoa(0) on the odd bit line Boa(0) is greater than the inhibit voltageVINH and the word lines Wa(0), Wa(y) in electrical communication withthe other resistive change elements O00 a, O0 ya on the odd bit lineBoa(0) are driven to the inhibit voltage VINH, leakage currents flowfrom the odd bit line Boa(0) through the other resistive change elementsO00 a, O0 ya and pull down the voltage VBoa(0) on the bit line Boa(0).It is noted that when the voltage VBoa(x) on the odd bit line Boa(x) isless than the inhibit voltage VINH and the word lines Wa(0), Wa(y) inelectrical communication with the other resistive change elements Ox0 a,Oxya on the odd bit line Boa(x) are driven to the inhibit voltage VINH,leakage currents flow into the odd bit line Boa(x) through the otherresistive change elements Ox0 a, Oxya and pull up the voltage VBoa(x) onthe odd bit line Boa(x). It is also noted that when the voltage VBoa(x)on the odd bit line Boa(x) is greater than the inhibit voltage VINH andthe word lines Wa(0), Wa(y) in electrical communication with the otherresistive change elements Ox0 a, Oxya on the odd bit line Boa(x) aredriven to the inhibit voltage VINH, leakage currents flow from the oddbit line Boa(x) through the other resistive change elements Ox0 a, Oxyaand pull down the voltage VBoa(x) on the bit line Boa(x). It is furthernoted that when voltages on the plurality of odd bit lines Boa(0)-Boa(x)are pulled up by leakage currents flowing into the plurality of odd bitlines Boa(0)-Boa(x), when voltages on the plurality of odd bit linesBoa(0)-Boa(a) are pulled down by leakage currents flowing from theplurality of bit lines Boa(0)-Boa(x), and when a voltage on at least oneodd bit line of the plurality of odd bit lines Boa(0)-Boa(x) is pulledup by leakage currents flowing into the at least one odd bit line and avoltage on at least one other odd bit line of the plurality of odd bitlines Boa(0)-Boa(x) is pulled down by leakage currents flowing from theat least one other odd bit line, the number of the word lines Wa(0),Wa(y) should be small enough to allow a margin to determine resistivestates of the odd resistive change elements O01 a, Ox1 a.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A proceeds, as similarlydiscussed above in step 412 of the flow chart 400, by determining theresistive states of the odd resistive change elements O01 a, Ox1 a basedon the voltages VGB3(0)-VGB3(x) on the plurality of global bit linesGB3(0)-GB3(x). As discussed above, a voltage indicative of a resistivestate of an odd resistive change element in the odd resistive changeelements O01 a, Ox1 a is generated on a global bit line in the pluralityof global bit lines GB3(0)-GB3(x) having the same column number as theodd resistive change element. The resistive state of the resistivechange element O01 a is determined by comparing the voltage VGB3(0) onwith global bit line GB3(0) with the inhibit voltage VINH on thereference line RL3 and the resistive state of the resistive changeelement Ox1 a is determined by comparing the voltage VGB3(x) on withglobal bit line GB3(x) with the inhibit voltage VINH on the referenceline RL3. For READ operations the inhibit voltage VINH is indicative ofthe intermediate resistance because the inhibit voltage VINH is equal tothe system voltage VDD minus a voltage calculated by multiplying theamount of current for a READ operation and the intermediate resistanceof 5.5MΩ. For example, when the system voltage VDD=2V, the inhibitvoltage VINH=1V, the amount of current for READ operations=1/5.5 μA, andthe intermediate resistance=5.5MΩ, VINH=2V−(1/5.5 μA×5.5MΩ)=1V.

When the voltage VGB3(0) on the global bit line GB3(0) is greater thanthe inhibit voltage (i.e. the voltage VGB3(0) on the global bit lineGB3(0)>VINH) the resistance of the resistive change element O01 a isless than the intermediate resistance (i.e. RO01 a<intermediateresistance, where RO01 a is the resistance of the resistive changeelement O01 a) and the resistive state of the resistive change elementO01 a is determined to be a low resistive state. When the voltageVGB3(0) on the global bit line GB3(0) is less than the inhibit voltageVINH (i.e. the voltage VGB3(0) on the global bit line GB3(0)<VINH) theresistance of the resistive change element O01 a is greater than theintermediate resistance (i.e. RO01 a>intermediate resistance, where RO01a is the resistance of the resistive change element OO1 a) and theresistive state of resistive change element OO1 a is determined to be ahigh resistive state.

When the voltage VGB3(x) on the global bit line GB3(x) is greater thanthe inhibit voltage (i.e. the voltage VGB3(x) on the global bit lineGB3(x)>VINH) the resistance of the resistive change element Ox1 a isless than the intermediate resistance (i.e. ROx1 a<intermediateresistance, where ROx1 a is the resistance of the resistive changeelement Ox1 a) and the resistive state of the resistive change elementOx1 a is determined to be a low resistive state. When the voltageVGB3(x) on the global bit line GB3(x) is less than the inhibit voltageVINH (i.e. the voltage VGB3(x) on the global bit line GB3(x)<VINH) theresistance of the resistive change element Ox1 a is greater than theintermediate resistance (i.e. ROx1 a>intermediate resistance, where ROx1a is the resistance of the resistive change element Ox1 a) and theresistive state of resistive change element Ox1 a is determined to be ahigh resistive state.

The sense amplifier 2000 receives the inhibit voltage VINH on thereference line RL3 and the voltage VGB3(0) on the global bit line GB3(0)and determines the resistive state of the resistive change element O01 aby comparing the inhibit voltage VINH on the reference line RL3 with thevoltage VGB3(0) on the global bit line GB3(0). The sense amplifier 2000outputs signals indicative of the resistive state of the resistivechange element O01 a on two outputs. When the voltage VGB3(0) on theglobal bit line GB3(0) is greater than the inhibit voltage VINH, thesense amplifier 2000 outputs signals indicating the resistive changeelement O01 a has a low resistive state. When the voltage VGB3(0) on theglobal bit line GB3(0) is less than the inhibit voltage VINH, the senseamplifier 2000 outputs signals indicating the resistive change elementO01 a has a high resistive state. The sense amplifier 2000 operates inthe same manner as the first sense amplifier 200 discussed above. It isnoted that providing the inhibit voltage VINH on the reference line RL3to the sense amplifier 2000 can increase the accuracy of determining theresistive state of the resistive change element O01 a because theinhibit voltage VINH on the reference line RL3 and the voltage VGB3(0)on the global bit line GB3(0) are subject to similar conditions.

The sense amplifier 200 x receives the inhibit voltage VINH on thereference line RL3 and the voltage VGB3(x) on the global bit line GB3(x)and determines the resistive state of the resistive change element Ox1 aby comparing the inhibit voltage VINH on the reference line RL3 with thevoltage VGB3(x) on the global bit line GB3(x). The sense amplifier 200 xoutputs signals indicative of the resistive state of the resistivechange element Ox1 a on two outputs. When the voltage VGB3(x) on theglobal bit line GB3(x) is greater than the inhibit voltage VINH, thesense amplifier 200 x outputs signals indicating the resistive changeelement Ox1 a has a low resistive state. When the voltage VGB3(x) on theglobal bit line GB3(x) is less than the inhibit voltage VINH, the senseamplifier 200 x outputs signals indicating the resistive change elementOx1 a has a high resistive state. The sense amplifier 200 x operates inthe same manner as the first sense amplifier 200 discussed above. It isnoted that providing the inhibit voltage VINH on the reference line RL3to the sense amplifier 200 x can increase the accuracy of determiningthe resistive state of the resistive change element O01 a because theinhibit voltage VINH on the reference line RL3 and the voltage VGB3(0)on the global bit line GB3(0) are subject to similar conditions.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A proceeds, as similarlydiscussed above in step 414 of the flow chart 400, by restoring neutralvoltage conditions for resistive change elements impacted by generatingvoltages indicative of resistive states of the odd resistive changeelements O01 a, Ox1 a. Neutral voltage conditions are restored forresistive change elements impacted by generating voltages indicative ofresistive states of the odd resistive change elements O01 a, Ox1 a byfloating the plurality of odd bit lines Boa(0)-Boa(x) and applying theinhibit voltage VINH to the word line Wa(1). The plurality of even bitlines Bea(0)-Bea(x) are already floating because the plurality of evenselection devices Nea0-Neax are turned off. The inhibit voltage VINH isalready applied to the word lines Wa(0), Wa(y) because the word linedriver circuits 110 da, 11 yda are already supplying the inhibit voltageVINH. The plurality of odd bit lines Boa(0)-Boa(x) are floated bydisconnecting the plurality of odd bit lines Boa(0)-Boa(x) from theplurality of global bit lines GB3(0)-GB3(x) by turning off the pluralityof odd selection devices Noa0-Noax. The plurality of odd selectiondevices Noa0-Noax are turned off by control logic, such as a processor,a controller, and a microcontroller, supplying a signal SSELo having alow level. The inhibit voltage VINH is applied to the word line Wa(1) bythe word line driver circuit 111 da driving the voltage on the word lineWa(1) to the inhibit voltage VINH. The word line driver circuit 111 dasupplies the inhibit voltage VINH based on the signal ITE1 a supplied bycontrol logic, such as a processor, a controller, and a microcontroller.Thus, the inhibit voltage VINH is applied to the plurality of word linesWa(0)-Wa(y) with the plurality of even bit lines Bea(0)-Bea(x) and theplurality of odd bit lines Boa(0)-Boa(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00 a-Oxya.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 416 of the flow chart 400, by biasing global bitlines impacted by generating voltages indicative of resistive states ofthe odd resistive change elements O01 a, Ox1 a. Global bit linesimpacted by generating voltages indicative of resistive states of theodd resistive change elements O01 a, Ox1 a are biased to the inhibitvoltage VINH by floating the plurality of global bit lines GB3(0)-GB3(x)and applying the inhibit voltage VINH to the plurality of global bitlines GB3(0)-GB3(x). The plurality of global bit lines GB3(0)-GB3(x) arefloated by disconnecting the plurality of global bit lines GB3(0)-GB3(x)from the plurality of odd bit lines Boa(0)-Boa(x) and disconnecting theplurality of global bit lines GB3(0)-GB3(x) from the plurality of buslines BL30-BL3 x. The plurality of global bit lines GB3(0)-GB3(x) arealready disconnected from the plurality of even bit lines Bea(0)-Bea(x)because the plurality of even selection devices Nea0-Neax are turnedoff. The plurality of global bit lines GB3(0)-GB3(x) may be disconnectedfrom the plurality of odd bit lines Boa(0)-Boa(x) as part of restoringneutral voltage conditions for resistive change elements impacted bygenerating voltages indicative of resistive states of the odd resistivechange elements O01 a, Ox1 a as discussed above. The plurality of globalbit lines GB3(0)-GB3(x) are disconnected from the plurality of bus linesBL30-BL3 x by turning off the plurality of PMOS transistors 180 g-18 xg.The plurality of PMOS transistors 180 g-18 xg are turned off by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal CDO having a high level. The inhibit voltage VINH isapplied to the plurality of global bit lines GB3(0)-GB3(x) byelectrically connecting the plurality of global bit lines GB3(0)-GB3(x)to a power supply, a voltage source, a driver circuit, or other devicethat supplies the inhibit voltage VINH by turning on the plurality ofNMOS transistors 130 k-13 xk. The plurality of NMOS transistors 130 k-13xk are turned on by control logic, such as a processor, a controller,and a microcontroller, supplying a signal KEEPe having a high level anda signal KEEPo having a high level.

SET VERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of resistive change elementarray 101 in the exemplary DDR compatible implementation of the firstexemplary architecture and SET VERIFY operations of even resistivechange elements in electrical communication with a word line in asection of resistive change element array 101 in the exemplary DDRcompatible implementation of the first exemplary architecture can beperformed in a similar manner to the READ operations of odd resistivechange elements in electrical communication with word line Wa(1)discussed above, but with each current source of the plurality ofcurrent sources 1600-160 x set to sink an amount of current for a SETVERIFY operation. The amount of current for a SET VERIFY operation isbased on the amount of current that would flow through a resistor havinga low resistance and having the system voltage VDD applied to oneterminal of the resistor and the inhibit voltage VINH applied to theother terminal of the resistor. The amount of current that would flowthrough a resistor having a low resistance and having the system voltageVDD applied to one terminal of the resistor and the inhibit voltage VINHapplied to the other terminal of the resistor can be approximated by thefollowing equation, I=(VDD−VINH)/Low Resistance. For example, when thelow resistance is 2MΩ, the system voltage VDD is 2V, and the inhibitvoltage VINH is 1V, each current source of the plurality of currentsources 1600-160 x is configured to sink an amount of current for a SETVERIFY operation that can be approximated as I=(2V−1V)/2MΩ=0.5 μA.

The low resistance sets an upper boundary for resistance values thatcorrespond with a low resistive state during SET VERIFY operations. Thelow resistance is a design variable that can be selected by a circuitdesigner and the circuit designer typically selects a low resistancegreater than a model resistance for a low resistive state of a resistivechange element so that resistive change elements can have resistancesgreater than the model resistance for the low resistive state and bedetermined to have a low resistive state during SET VERIFY operations.For example, when a model resistance for a low resistive state of aresistive change element is 1MΩ, a circuit designer can select a lowresistance of 2MΩ so that resistive change elements having a resistanceless than approximately 2MΩ are determined to have a low resistive stateduring SET VERIFY operations. It is noted that the circuit designertypically selects a low resistance greater than a model resistance for alow resistive state of a resistive change element and less than anintermediate resistance for READ operations.

RESET VERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of resistive change elementarray 101 in the exemplary DDR compatible implementation of the firstexemplary architecture and RESET VERIFY operations of even resistivechange elements in electrical communication with a word line in asection of resistive change element array 101 in the exemplary DDRcompatible implementation of the first exemplary architecture can beperformed in a similar manner to the READ operations of odd resistivechange elements in electrical communication with word line Wa(1)discussed above, but with each current source of the plurality ofcurrent sources 1600-160 x set to sink an amount of current for a RESETVERIFY operation. The amount of current for a RESET VERIFY operation isbased on the amount of current that would flow through a resistor havinga high resistance and having the system voltage VDD applied to oneterminal of the resistor and the inhibit voltage VINH applied to theother terminal of the resistor. The amount of current that would flowthrough a resistor having a high resistance and having the systemvoltage VDD applied to one terminal of the resistor and the inhibitvoltage VINH applied to the other terminal of the resistor can beapproximated by the following equation, I=(VDD−VINH)/High Resistance.For example, when the high resistance is 9MΩ, the system voltage VDD is2V, and the inhibit voltage VINH is 1V, each current source of theplurality of current sources 1600-160 x is configured to sink an amountof current for a RESET VERIFY operation that can be approximated asI=(2V−1V)/9MΩ=0.11 μA.

The high resistance sets an upper boundary for resistance values thatcorrespond with a high resistive state during RESET VERIFY operations.The high resistance is a design variable that can be selected by acircuit designer and the circuit designer typically selects a highresistance less than a model resistance for a high resistive state of aresistive change element so that resistive change elements can haveresistances less than the model resistance for the high resistive stateand be determined to have a high resistive state during RESET VERIFYoperations. For example, when a model resistance for a high resistivestate of a resistive change element is 10MΩ, a circuit designer canselect a high resistance of 9MΩ so that resistive change elements havinga resistance greater than approximately 9MΩ are determined to have ahigh resistive state during RESET VERIFY operations. It is noted thatthe circuit designer typically selects a high resistance less than amodel resistance for a high resistive state of a resistive changeelement and greater than an intermediate resistance for READ operations.

Referring now to FIG. 5A, a second exemplary architecture forprogramming and accessing resistive change elements is illustrated in asimplified schematic diagram. The second exemplary architecture includesa resistive change element array 100, a plurality of global bit linesGB4(0)-G4(x), word line driver circuitry 101, a reference line RL4, areference line connection circuit 102, a keeper circuit 103, a resistor501, a global bit line connection circuit 502, a bus line BL4, a writebuffer circuit 105, a current source 106, a first input device 503, asecond input device 504, a capacitor 505, and a sense device 506. Theresistive change element array 100, the plurality of global bit linesGB4(0)-G4(x), the word line driver circuitry 101, the reference lineconnection circuit 102, the keeper circuit 103, the write buffer circuit105, and the current source 106 have similar structure to the resistivechange element array 100, the plurality of global bit linesGB1(0)-GB1(x), the word line driver circuitry 101, the reference lineconnection circuit 102, the keeper circuit 103, the write buffer circuit105, and the current source 106 as discussed above with respect to thefirst exemplary architecture for programming and accessing resistivechange elements. Therefore, the resistive change element array 100, theword line driver circuitry 101, the reference line connection circuit102, the keeper circuit 103, the write buffer circuit 105, and thecurrent source 106 are not discussed in detail with respect to thesecond exemplary architecture for programming and accessing resistivechange elements.

It is noted that although the second exemplary architecture is shown inFIG. 5A including one bus line, one write buffer circuit, one currentsource, one first input device, one second input device, and one sensedevice, the second exemplary architecture can include multiple buslines, multiple write buffer circuits, multiple current sources,multiple first input devices, multiple second input devices, andmultiple sense devices. For example, the second exemplary architecturecan include multiple bus lines, multiple write buffer circuits, multiplecurrent sources, multiple first input devices, and multiple sensedevices so that multiple resistive change elements can be programmed tothe same resistive state at the same time and so that multiple resistivechange elements can be accessed at the same time. For example, tofacilitate compatibility with memory functionality where programmingoperations program multiple bits of data at the same time and accessingoperations access multiple bits of data at the same time, such as doubledata rate (DDR) memory functionality, the second exemplary architecturecan include one bus line, one write buffer circuit, one current source,one first input device, and one sense device for each global bit line inthe plurality of global bit lines GB4(0)-GB4(x). In the above examplewhere the second exemplary architecture includes one bus line, one writebuffer circuit, one current source, one first input device, and onesense device for each global bit line in the plurality of global bitlines GB4(0)-GB4(x), a circuit designer may select the number of globalbit lines based on the number of bits of data to be accessed at the sametime, such as 32 global bit lines so that 32 bits of data can beaccessed at the same time and 64 global bit lines so that 64 bits ofdata can be accessed at the same time. It is also noted that when thesecond exemplary architecture includes multiple sense devices, thesecond exemplary architecture can include a second input devices foreach of the multiple sense devices or the second exemplary architecturecan include fewer second input devices than sense devices because secondinput devices can be shared between sense devices as discussed below.

Further, although the second exemplary architecture is shown in FIG. 5Aincluding a resistive change element array 100 having one section inelectrical communication with the plurality of global bit linesGB4(0)-GB4(x), the second exemplary architecture can include a resistivechange element array having multiple sections in electricalcommunication with the plurality of global bit lines GB4(0)-GB4(x) alongwith word line driver circuitry for each of the multiple sections and areference line connection circuit for each of the multiple sections. Forexample, the second exemplary architecture can include a resistivechange element array having two sections in electrical communicationwith the plurality of global bit lines GB4(0)-GB4(x), word line drivercircuitry for each section and a reference line connection circuit foreach section. In the above example, when the resistive change elementarray includes two sections having the same number of resistive changeelements, the amount of data storage may be doubled as compared to aresistive change element array including one section having the samenumber of resistive change elements as one of the two sections withoutdoubling the chip area consumed by the second exemplary architecturebecause the resistor 501, the keeper circuit 103, the global bit lineconnection circuit 502, the bus line BL4, the write buffer circuit 105,the current source 106, the first input device 503, the second inputdevice 504, the capacitor 505, and the sense device 506 can be shared bythe two sections. It is also noted that the chip area consumed by thesecond exemplary architecture also can be reduced by locating word linedriver circuitry for each section and a reference line connectioncircuit for each section below the resistive change element array. It isfurther noted that the second exemplary architecture can includemultiple bus lines, multiple write buffer circuits, multiple currentsources, multiple first input devices, multiple sense devices, and aresistive change element array having multiple sections in electricalcommunication with the plurality of global bit lines GB4(0)-GB4(x) andthat the multiple bus lines, multiple write buffer circuits, multiplecurrent sources, multiple first input devices, and multiple sensedevices can be shared by the multiple sections.

The global bit line connection circuit 502 is in electricalcommunication with the reference line RL4, the second input device 504,the plurality of global bit lines GB4(0)-GB4(x), and the bus line BL4.The global bit line connection circuit 502 is configured to electricallyconnect the reference line RL4 and the second input device 504 and toelectrically connect the plurality of global bit lines GB4(0)-GB4(x) andthe bus line BL4. An exemplary circuit for the global bit lineconnection circuit 502 is discussed below with respect to FIGS. 5B-1 and5B-2. However, the global bit line connection circuit 502 is not limitedto the global bit line connection circuit 502 discussed below withrespect to FIGS. 5B-1 and 5B-2. For example, the global bit lineconnection circuit 502 can be other circuits configured to electricallyconnect the reference line RL4 and the second input device 504 and toelectrically connect the plurality of global bit lines GB4(0)-GB4(x) andthe bus line BL4. The global bit line connection circuit 502 is inelectrical communication with the reference line RL4 through theresistor 501. The resistor 501 is included in the second exemplaryarchitecture to increase the impedance as seen from the second inputdevice 504 so that the impedance as seen from the second input device504 generally corresponds with the impedance as seen from the firstinput device 503, however, when the resistor 501 is not needed theresistor 501 may be omitted. For example, the resistor 501 may have aresistance that is an average of a model resistance for a low resistivestate of a resistive change element and a model resistance for a highresistive state of a resistive change element because the impedance asseen from the first input device 503 during an accessing operation isdominated by a resistance of the resistive change element beingaccessed. In the above example, when the model resistance for a lowresistive state of a resistive change element is 1MΩ and the modelresistance for a high resistive state of a resistive change element is10MΩ the resistor 501 may have a resistance=(1MΩ+10MΩ)/2=5.5MΩ.

The first input device 503 is in electrical communication with the busline BL4, the sense amplifier 506, and a power supply, a voltage source,a driver circuit, or other device that supplies a desired voltage. Thefirst input device 503 is configured to supply the voltage on the busline BL4 or the desired voltage to the sense device 506. An exemplarycircuit for the first input device 503 is discussed below with respectto FIGS. 5B-1 and 5B-2. However, the first input device 503 is notlimited to the first input device discussed below with respect to FIGS.5B-1 and 5B-2. For example, the first input device 503 can be othercircuits configured to supply the voltage on the bus line BL4 or thedesired voltage to the sense device 506.

The second input device 504 is in electrical communication with theglobal bit line connection circuit 502, the sense amplifier 506, and apower supply, a voltage source, a driver circuit, or other device thatsupplies a desired voltage. The second input device 504 is configured tosupply a voltage supplied by the global bit line connection circuit 502or the desired voltage to the sense device 506. An exemplary circuit forthe second input device 504 is discussed below with respect to FIGS.5B-1 and 5B-2. However, the second input device 504 is not limited tothe second input device discussed below with respect to FIGS. 5B-1 and5B-2. For example, the second input device 504 can be other circuitsconfigured to supply a voltage supplied by the global bit lineconnection circuit 502 or the desired voltage to the sense device 506.

The capacitor 505 has a first terminal and a second terminal. The firstterminal of the capacitor 505 is in electrical communication with thereference line RL4 and the second terminal of the capacitor 505 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The capacitor505 can reduce noise on the reference line RL4 by providing a path fornoise to flow to 0 volts or ground. Alternatively, the capacitor 505 canbe replaced with a plurality of capacitors, with each capacitor having afirst terminal in electrical communication with the reference line RL4and a second terminal in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies 0 voltsor ground. Alternatively, the capacitor 505 can be omitted.

The sense device 506 is in electrical communication with the first inputdevice 503 and the second input device 504 and the sense device 506 isconfigured to generate at least one output voltage based on a voltagesupplied by the first input device 503 and a voltage supplied by thesecond input device 504. Exemplary sense amplifiers for the sense device506 are discussed below with respect to FIGS. 5B-1, 5B-2, 6, and 7.However, the sense device 506 is not limited to the sense amplifiersdiscussed below with respect to FIGS. 5B-1, 5B-2, 6, and 7. For example,the sense device 506 can be a component that generates at least oneoutput voltage based on at least two input voltages, such as adifferential amplifier and a sense amplifier other than the senseamplifiers discussed below with respect to FIGS. 5B-1, 5B-2, 6, and 7.

Referring now to FIGS. 5B-1 and 5B-2, an exemplary implementation of thesecond exemplary architecture for programming and accessing resistivechange elements is illustrated in a simplified schematic diagram. Theexemplary implementation of the second exemplary architecture includes aresistive change element array 100, a plurality of global bit linesGB5(0)-GB5(x), word line driver circuitry 110, a reference line RLS, areference line connection circuit 120, a resistor 530, a bus line BLS, akeeper circuit 130, a global bit line connection circuit 540, a writebuffer circuit 150, a current source 160, a first input device 510, asecond input device 520, a capacitor 580, and a sense amplifier 550. Theresistive change element array 100, the plurality of global bit linesGB5(0)-GB5(x), the word line driver circuitry 110, the reference lineconnection circuit 120, the keeper circuit 130, the write buffer circuit150, and the current source 160 have a similar structure to theresistive change element array 100, the plurality of global bit linesGB1(0)-GB1(x), the word line driver circuitry 110, the reference lineconnection circuit 120, the keeper circuit 130, the write buffer circuit150, and the current source 160 as discussed above with respect to theexemplary implementation of the first exemplary architecture forprogramming and accessing resistive change elements. Therefore, theresistive change element array 100, the plurality of global bit linesGB5(0)-GB5(x), the word line driver circuitry 110, the reference lineconnection circuit 120, the keeper circuit 130, the write buffer circuit150, and the current source 160 are not discussed in detail with respectto the exemplary implementation of the second exemplary architecture forprogramming and accessing resistive change elements.

The resistor 530 is included in the exemplary implementation of thesecond exemplary architecture to increase the impedance as seen from thesecond input device 520 so that the impedance as seen from the secondinput device 520 generally corresponds with the impedance as seen fromthe first input device 510, however, when the resistor 530 is not neededthe resistor 530 may be omitted. For example, the resistor 530 may havea resistance that is an average of a model resistance for a lowresistive state of a resistive change element and a model resistance fora high resistive state of a resistive change element because theimpedance as seen from the first input device 510 during an accessingoperation is dominated by a resistance of the resistive change elementbeing accessed. In the above example, when the model resistance for alow resistive state of a resistive change element is 1MΩ and the modelresistance for a high resistive state of a resistive change element is10MΩ the resistor 530 may have a resistance =(1MΩ+10MΩ)/2=5.5MΩ.

The global bit line connection circuit 540 includes a first plurality ofPMOS transistors 540 g-54 xg having drain terminals, gate terminals, andsource terminals and a second plurality of PMOS transistors 540 r-54 xrhaving drain terminals, gate terminals, and source terminals. Thenumbering convention for the first plurality of PMOS transistors 540g-54 xg includes a column number as the next to last referencecharacter, the numbering convention for the second plurality of PMOStransistors 540 r-54 xr includes a column number as the next to lastreference character, and the numbering convention for the plurality ofglobal bit lines GB5(0)-GB5(x) begins with letters and number GB5indicating the line is a global bit line followed by a column number inparentheses. The drain terminals of the first plurality of PMOStransistors 540 g-54 xg are in electrical communication with the busline BLS. The gate terminals of the first plurality of PMOS transistors540 g-54 xg are in electrical communication with control logic, such asa processor, a controller, and a microcontroller. The source terminalsof the first plurality of PMOS transistors 540 g-54 xg are in electricalcommunication with the global bit lines GB5(0)-GB5(x) having the samecolumn number. The drain terminals of the second plurality of PMOStransistors 540 r-54 xr are in electrical communication with the secondinput device 520. The gate terminals of the second plurality of PMOStransistors 540 r-54 xr are in electrical communication with controllogic, such as a processor, a controller, and a microcontroller. Thesource terminals of the second plurality of PMOS transistors 540 r-54 xrare in electrical communication with the reference line RL5 through theresistor 530. Alternatively, the first plurality of PMOS transistors 540g-54 xg can be other types of field effect transistors, such as carbonnanotube field effect transistors (CNTFETs), SiGE FETs, fully-depletedsilicon-on-insulator FETs, or multiple gate field effect transistorssuch as FinFETs, and/or the second plurality of PMOS transistors 540r-54 xr can be other types of field effect transistors, such as carbonnanotube field effect transistors (CNTFETs), SiGE FETs, fully-depletedsilicon-on-insulator FETs, or multiple gate field effect transistorssuch as FinFETs. It is noted that when field effect transistors that donot require a semiconductor substrate are used this enables the fieldeffect transistors to be fabricated on insulator material, andadditionally, enables the field effect transistors to be stacked toreduce the amount of chip area consumed by the first plurality of PMOStransistors 540 g-54 xg and the second plurality of PMOS transistors 540r-54 xr.

The global bit line connection circuit 540 includes the second pluralityof PMOS transistors 540 r-54 xr in electrical communication with thereference line RL5 and the second input device 520 so that the noisebehavior of a voltage on the reference line RL5 received by the secondinput device 520 is similar to the noise behavior of a voltage on thebus line BL5 received by the first input device 510. The number of PMOStransistors in the first plurality of PMOS transistors 540 g-54 xg andthe number of PMOS transistors in the second plurality of PMOStransistors 540 r-54 xr are generally the same number. The firstplurality of PMOS transistors 540 g-54 xg and the second plurality ofPMOS transistors 540 r-54 xr receive a plurality of signals YD0-YDx forcontrolling current flow through the first plurality of PMOS transistors540 g-54 xg and the second plurality of PMOS transistors 540 r-54 xr.PMOS transistors in the first plurality of PMOS transistors 540 g-54 xgand PMOS transistors in the second plurality of PMOS transistors 540r-54 xr having the same column numbers receive the same signals.

The capacitor 580 has a first terminal and a second terminal. The firstterminal of the capacitor 580 is in electrical communication with thereference line RL5 and the second terminal of the capacitor 580 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The capacitor580 can reduce noise on the reference line RL5 by providing a path fornoise to flow to 0 volts or ground. Alternatively, the capacitor 580 canbe replaced with a plurality of capacitors, with each capacitor having afirst terminal in electrical communication with the reference line RL5and a second terminal in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies 0 voltsor ground. Alternatively, the capacitor 580 can be omitted.

The first input device 510 includes a first PMOS transistor 512 having adrain terminal, a gate terminal, and a source terminal and a second PMOStransistor 514 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first PMOS transistor 512 is inelectrical communication with a first input terminal of the senseamplifier 550, the gate terminal of the first PMOS transistor 512 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive an initialization signalINIT, and the source terminal of the first PMOS transistor 512 is inelectrical communication with the bus line BLS. The drain terminal ofthe second PMOS transistor 514 is in electrical communication with afirst input terminal of the sense amplifier 550, the gate terminal ofthe second PMOS transistor 514 is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive a complementary initialization signal INITB, and the sourceterminal of the second PMOS transistor 514 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies an inhibit voltage VINH.

The second input device 520 includes a first PMOS transistor 522 havinga drain terminal, a gate terminal, and a source terminal and a secondPMOS transistor 524 having a drain terminal, a gate terminal, and asource terminal. The drain terminal of the first PMOS transistor 522 isin electrical communication with a second input terminal of the senseamplifier 550 and the capacitor 580, the gate terminal of the first PMOStransistor 522 is in electrical communication with control logic, suchas a processor, a controller, and a microcontroller, to receive aninitialization signal INIT, and the source terminal of the first PMOStransistor 522 is in electrical communication with the global bit lineconnection circuit 540. The drain terminal of the second PMOS transistor524 is in electrical communication with a second input terminal of senseamplifier 550 and the capacitor 580, the gate terminal of the secondPMOS transistor 524 is in electrical communication with control logic,such as a processor, a controller, and a microcontroller, to receive acomplementary initialization signal INITB, and the source terminal ofthe second PMOS transistor 524 is in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies an inhibit voltage VINH.

The sense amplifier 550 has a first input terminal in electricalcommunication with the first input device 510, a second input terminalin electrical communication with the second input device 520, and twooutput terminals. The two output terminals can be in electricalcommunication with a bus, a buffer, a level shift circuit, a testcircuit, or control logic such as a processor, a controller, and amicrocontroller. The sense amplifier 550 can be a second sense amplifier600 or a third sense amplifier 700. The second sense amplifier 600 isdiscussed below with respect to FIG. 6. The third sense amplifier 700 isdiscussed below with respect to FIG. 7.

As shown in FIGS. 5B-1 and 5B-2, the first input device 510 and thesecond input device 520 are located outside of the sense amplifier 550and this permits the first input device 510 and/or the second inputdevice 520 to be shared with multiple sense amplifiers. For example,when the exemplary implementation of the second exemplary architectureadditionally includes another sense amplifier for comparing the voltageon the reference line RL5 and a voltage on another bus line, the secondinput device 520 can be shared by the sense amplifier 550 and theanother sense amplifier. For example, when the exemplary implementationof the second exemplary architecture additionally includes another senseamplifier for comparing a voltage on another reference line and thevoltage on the bus line BLS, the first input device 510 can be shared bythe sense amplifier 550 and the another sense amplifier. In the aboveexamples, where the sense amplifier 550 and another sense amplifiershare an input device the exemplary implementation of the secondexemplary architecture includes three input devices instead of fourinput devices. Sharing input devices between multiple sense amplifierscan reduce the number of the input devices included in an architectureand thus reduce the amount of chip area consumed. Additionally, sharinginput devices between multiple sense amplifiers can reduce the number ofinput devices in electrical communication with a reference line and/or abus line. Further, sharing input devices between multiple senseamplifiers can reduce the number of transistors that are supplied withsignals by control logic, such as a processor, a controller, and amicrocontroller.

Referring now to FIG. 5C, an exemplary arrangement for two senseamplifiers sharing an input device is illustrated. The exemplaryarrangement includes two sense amplifiers 550 a and 550 b, two firstinput devices 560 a, 560 b, and a second input device 570. In theexemplary arrangement of FIG. 5C, the sense amplifier 550 a is used forcomparing a voltage on a bus line BL51 and a voltage on a reference lineRL51 and the sense amplifier 550 b is used for comparing a voltage on abus line BL52 and a voltage on the reference line RL51. Each of the twosense amplifiers 550 a, 550 b has a first input terminal, a second inputterminal, and two output terminals.

The first input device 560 a includes a first PMOS transistor 562 ahaving a drain terminal, a gate terminal, and a source terminal and asecond PMOS transistor 564 a having a drain terminal, a gate terminal,and a source terminal. The drain terminal of the first PMOS transistor562 a is in electrical communication with a first input terminal of thesense amplifier 550 a, the gate terminal of the first PMOS transistor562 a is in electrical communication with control logic, such as aprocessor, a controller, and a microcontroller, to receive aninitialization signal INIT, and the source terminal of the first PMOStransistor 562 a is in electrical communication with the bus line BL51.The drain terminal of the second PMOS transistor 564 a is in electricalcommunication with a first input terminal of the sense amplifier 550 a,the gate terminal of the second PMOS transistor 564 a is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive a complementary initialization signalINITB, and the source terminal of the second PMOS transistor 564 a is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies an inhibit voltage VINH.

The first input device 560 b includes a first PMOS transistor 562 bhaving a drain terminal, a gate terminal, and a source terminal and asecond PMOS transistor 564 b having a drain terminal, a gate terminal,and a source terminal. The drain terminal of the first PMOS transistor562 b is in electrical communication with a first input terminal of thesense amplifier 550 b, the gate terminal of the first PMOS transistor562 b is in electrical communication with control logic, such as aprocessor, a controller, and a microcontroller, to receive aninitialization signal INIT, and the source terminal of the first PMOStransistor 562 b is in electrical communication with the bus line BL52.The drain terminal of the second PMOS transistor 564 b is in electricalcommunication with a first input terminal of the sense amplifier 550 b,the gate terminal of the second PMOS transistor 564 b is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive a complementary initialization signalINITB, and the source terminal of the second PMOS transistor 564 b is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies an inhibit voltage VINH.

The second input device 570 includes a first PMOS transistor 572 havinga drain terminal, a gate terminal, and a source terminal and a secondPMOS transistor 574 having a drain terminal, a gate terminal, and asource terminal. The drain terminal of the first PMOS transistor 572 isin electrical communication with a second input terminal of the senseamplifier 550 a and a second input terminal of the sense amplifier 550b, the gate terminal of the first PMOS transistor 572 is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive an initialization signal INIT, and thesource terminal of the first PMOS transistor 572 is in electricalcommunication with the reference line RL51. The drain terminal of thesecond PMOS transistor 574 is in electrical communication with a secondinput terminal of the sense amplifier 550 a and a second input terminalof the sense amplifier 550 b, the gate terminal of the second PMOStransistor 574 is in electrical communication with control logic, suchas a processor, a controller, and a microcontroller, to receive acomplementary initialization signal INITB, and the source terminal ofthe second PMOS transistor 574 is in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies an inhibit voltage VINH. The second input device 570 is sharedbetween the two sense amplifiers 550 a, 550 b by having the drainterminals of the first PMOS transistor 572 and the second PMOStransistor 574 in electrical communication with the second inputterminal of the sense amplifier 550 a and the second input terminal ofthe sense amplifier 550 b.

PROGRAMMING operations of resistive change elements in the exemplaryimplementation of the second exemplary architecture shown in FIGS. 5B-1and 5B-2 are performed in a similar manner to PROGRAMMING operations ofresistive change elements in the exemplary implementation of the firstexemplary architecture. PROGRAMMING operations of resistive changeelements in the exemplary implementation of the first exemplaryarchitecture are discussed above. Therefore, PROGRAMMING operations ofresistive change elements in the exemplary implementation of the secondexemplary architecture shown in FIGS. 5B-1 and 5B-2 are not discussed indetail below. READ operations, SET VERIFY operations, and RESET VERIFYoperations of resistive change elements in the exemplary implementationof the second exemplary architecture of FIGS. 5B-1 and 5B-2 arediscussed below with respect to FIGS. 5D-1 and 5D-2 that show currentflow during a READ operation of resistive change element O01 whenresistive change element O01 has a low resistive state and FIGS. 5E-1and 5E-2 that show current flow during a READ operation of resistivechange element O01 when resistive change element O01 has a highresistive state. It is noted that although READ operations, SET VERIFYoperations, and RESET VERIFY operations of resistive change element O01in the exemplary implementation of the second exemplary architecture ofFIGS. 5B-1 and 5B-2 will be explained in detail below, READ operations,SET VERIFY operations, and RESET VERIFY operations of each resistivechange element in the exemplary implementation of the second exemplaryarchitecture of FIGS. 5B-1 and 5B-2 can be performed in a similar mannerto resistive change element O01.

Referring now to FIGS. 5D-1 and 5D-2, a READ operation of the resistivechange element O01 starts, as similarly discussed above in step 402 ofthe flow chart 400, by providing neutral voltage conditions for theplurality of resistive change elements E00-Oxy in the resistive changeelement array 100. The neutral voltage conditions are provided for theplurality of resistive change elements E00-Oxy by floating the pluralityof even bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) and applying the inhibit voltage VINH to the plurality ofword lines W(0)-W(y) with the plurality of even bit lines Be(0)-Be(x)and the plurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy. Floating a linerefers to electrically connecting the line such that a voltage on theline exists due to a line capacitance of the line. The plurality of evenbit lines Be(0)-Be(x) are floated by disconnecting the plurality of evenbit lines Be(0)-Be(x) from the plurality of global bit linesGB5(0)-GB5(x) by turning off the plurality of even selection devicesNe0-Nex. The plurality of even selection devices Ne0-Nex are turned offby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level. Theplurality of odd bit lines Bo(0)-Bo(x) are floated by disconnecting theplurality of odd bit lines Bo(0)-Bo(x) from the plurality of global bitlines GB5(0)-GB5(x) by turning off the plurality of odd selectiondevices No0-Nox. The plurality of odd selection devices No0-Nox areturned off by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a low level. It isnoted that control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELe having a low level and asignal SSELo having a low level also turns off the first NMOS transistor121 and the second NMOS transistor 122 of the reference line connectioncircuit 120.

The inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) by the word line driver circuitry 110 driving voltages on theplurality of word lines W(0)-W(y) to the inhibit voltage VINH. Theplurality of word line driver circuits 110 d-11 yd receive the systemvoltage VDD on the first power terminals because the first NMOStransistor 110 p is turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying the signal S0 having a highlevel and receive the inhibit voltage VINH on the second power terminalsbecause the second NMOS transistor 111 p is turned on by the controllogic supplying the signal S1 having a high level. The plurality of wordline driver circuits 110 d-11 yd supply the inhibit voltage VINH basedon the plurality of signals ITE0-ITEy supplied by control logic, such asa processor, a controller, and a microcontroller. The plurality of sinktransistors 110 s-11 ys are turned off because control logic, such as aprocessor, a controller, and a microcontroller, supplies the pluralityof signals SK0-Sky having low levels.

Driving the plurality of word lines W(0)-W(y) to the inhibit voltageVINH with the plurality of even bit lines Be(0)-Be(x) and the pluralityof odd bit lines Bo(0)-Bo(x) floating causes voltages on the pluralityof word lines W(0)-W(y), voltages on the plurality of even bit linesBe(0)-Be(x), and voltages on the plurality of odd bit lines Bo(0)-Bo(x)to be approximately equal to the inhibit voltage VINH. Voltages on theplurality of even bit lines Be(0)-Be(x) and voltages on the plurality ofodd bit lines Bo(0)-Bo(x) are approximately equal to the inhibit voltageVINH because currents flow from the plurality of word lines W(0)-W(y)through the plurality of resistive change elements E00-Oxy into theplurality of even bit lines Be(0)-Be(x) and the plurality of odd bitlines Bo(0)-Bo(x). The inhibit voltage VINH exists on the plurality ofeven bit lines Be(0)-Be(x) and the plurality of odd bit linesBo(0)-Bo(x) due to line capacitances because the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x) arefloating. Thus, driving voltages on the plurality of word linesW(0)-W(y) to the inhibit voltage VINH with the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x)floating results in application of voltages approximately equal to theinhibit voltage VINH to the top electrodes and the bottom electrodes ofthe resistive change elements in the plurality of resistive changeelements E00-Oxy. Additionally, driving the plurality of word linesW(0)-W(y) to the inhibit voltage VINH with the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00-Oxy to be approximately 0volts.

The READ operation of the resistive change element O01 continues, assimilarly discussed above in step 404 of the flow chart 400, by biasingthe plurality of global bit lines GB5(0)-GB5(x). The plurality of globalbit lines GB5(0)-GB5(x) are biased to the inhibit voltage VINH byfloating the plurality of global bit lines GB5(0)-GB5(x) and applyingthe inhibit voltage VINH to the plurality of global bit linesGB5(0)-GB5(x). The plurality of global bit lines GB5(0)-GB5(x) arefloated by disconnecting the plurality of global bit lines GB5(0)-GB5(x)from the plurality of even bit lines Be(0)-Be(x), the plurality of oddbit lines Bo(0)-Bo(x), and the bus line BL5. The plurality of global bitlines GB5(0)-GB5(x) may be disconnected from the plurality of even bitlines Be(0)-Be(x) and the plurality of odd bit lines Bo(0)-Bo(x) as partof providing neutral voltage conditions for the plurality of resistivechange elements E00-Oxy as discussed above. The plurality of global bitlines GB5(0)-GB5(x) are disconnected from the bus line BL5 by turningoff the first plurality of PMOS transistors 540 g-54 xg in the globalbit line connection circuit 540. The first plurality of PMOS transistors540 g-54 xg are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a plurality of signalsYD0-YDx having high levels. The inhibit voltage VINH is applied to theplurality of global bit lines GB5(0)-GB5(x) by electrically connectingthe plurality of global bit lines GB5(0)-GB5(x) to a power supply, avoltage source, a driver circuit, or other device that supplies theinhibit voltage VINH by turning on the plurality of NMOS transistors 130k-13 xk in the keeper circuit 130. The plurality of NMOS transistors 130k-13 xk are turned on by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal KEEPe having ahigh level and a signal KEEPo having a high level. It is noted thatcontrol logic, such as a processor, a controller, and a microcontroller,supplying a plurality of signals YD0-YDx having high levels also turnsoff the second plurality of PMOS transistors 540 r-54 xr in the globalbit line connection circuit 540. It is further noted that the referenceline RL5 floats because the second plurality of PMOS transistors 540r-54 xr, the first NMOS transistor 121, and the second NMOS transistor122 are turned off.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 406 of the flow chart 400, byselecting the resistive change element O01 from the plurality ofresistive change elements E00-Oxy. The resistive change element O01 isselected from the plurality of resistive change elements E00-Oxy bycontrol logic, such as a processor, a controller, and a microcontroller.The resistive change elements E00-Ox0, E01, Ex1-Ox1 and E0 y-Oxy in theplurality of resistive change elements E00-Oxy that are not selected arereferred to as unselected resistive change elements.

The READ operation of the resistive change element O01 continues, assimilarly discussed above in step 408 of the flow chart 400, bypreparing the exemplary implementation of the second exemplaryarchitecture for determining a resistive state of the resistive changeelement O01. The exemplary implementation of the second exemplaryarchitecture is prepared for determining a resistive state of theresistive change element O01 by changing electrical connections of thereference line RL5, driving the voltage on the reference line RL5 to theinhibit voltage VINH, changing electrical connections of the odd bitline Bo(0), changing electrical connections of the global bit lineGB5(0), and disconnecting a power supply, a voltage source, a drivercircuit, or the device that supplies the inhibit voltage VINH from theglobal bit line GB5(0). The electrical connections of the reference lineRL5 are changed so that the reference line RL5 is in electricalcommunication with the second input device 520. The reference line RL5is electrically connected to the second input device 520 by turning onthe PMOS transistor 540 r. The PMOS transistor 540 r is turned on bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal YD0 having a low level. The voltage on the referenceline RL5 is driven to the inhibit voltage VINH by electricallyconnecting the reference line RL5 through the second NMOS transistor 122of the reference line connection circuit 120 and the second NMOStransistor 111 p of the word line driver circuitry 110 to a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH. The second NMOS transistor 122 isturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a high level and, asdiscussed above with respect to providing neutral voltage conditions forthe plurality of resistive change elements E00-Oxy in the resistivechange element array 100, the second NMOS transistor 111 p of the wordline driver circuitry 110 is turned on.

The electrical connections of the odd bit line Bo(0) and the electricalconnections of the global bit line GB5(0) are changed and a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the global bitline GB5(0) so that a voltage indicative of the resistive state of theresistive change element O01 can be generated on the odd bit line Bo(0),the global bit line GB5(0), and the bus line BL5. The electricalconnections of the odd bit line Bo(0) are changed so that the odd bitline Bo(0) is in electrical communication with the global bit lineGB5(0). The odd bit line Bo(0) is electrically connected to the globalbit line GB5(0) by turning on the odd selection device No0. The oddselection device No0 is turned on by control logic, such as a processor,a controller, and a microcontroller, supplying a signal SSELo having ahigh level. The odd bit line Bo(0) may be electrically connected to theglobal bit line GB5(0) as part of driving the voltage on the referenceline RL5 to the inhibit voltage VINH as discussed above. It is notedthat the plurality of odd selection devices No0-Nox are turned on by thecontrol logic supplying a signal SSELo having a high level, and thus,the plurality of odd bit lines Bo(0)-Bo(x) are electrically connected tothe plurality of global bit lines GB5(0)-GB5(x).

The electrical connections of the global bit line GB5(0) are changed sothat the global bit line GB5(0) is in electrical communication with theodd bit line Bo(0) and the bus line BL5. The global bit line GB5(0) iselectrically connected to the odd bit line Bo(0) by turning on the oddselection device No0 as discussed above and the global bit line GB5(0)may be electrically connected to the odd bit line Bo(0) as part ofdriving the voltage on the reference line RL5 to the inhibit voltageVINH as discussed above. The global bit line GB5(0) is electricallyconnected to the bus line BL5 by turning on the PMOS transistor 540 g.The PMOS transistor 540 g is turned on by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signal YD0having a low level. The global bit line GB5(0) may be electricallyconnected to the bus line BL5 as part of electrically connecting thereference line RL5 to the second input device 520 as discussed above. Apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH is disconnected from the global bitline GB5(0) by turning off the NMOS transistor 130 k. The NMOStransistor 130 k is turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal KEEPe having a lowlevel. It is noted that the control logic supplying a signal KEEPehaving a low level also turns off NMOS transistors in the plurality ofNMOS transistors 130 k-13 xk in electrical communication with global bitlines having even column numbers and disconnects global bit lines havingeven column numbers from a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH.

The READ operation of the resistive change element O01 continues, assimilarly discussed above in step 410 of the flow chart 400, bygenerating a voltage indicative of a resistive state of the resistivechange element O01. The voltage indicative of the resistive state of theresistive change element O01 is generated on the odd bit line Bo(0), theglobal bit line GB5(0), and the bus line BL5 by driving the voltage onthe word line W(1) to the system voltage VDD and sinking an amount ofcurrent for a READ operation from the bus line BL5. As discussed above,providing neutral voltage conditions for the plurality of resistivechange elements E00-Oxy causes voltages on the plurality of word linesW(0)-W(y), voltages on the plurality of even bit lines Be(0)-Be(x), andvoltages on the plurality of odd bit lines Bo(0)-Bo(x) to beapproximately equal to the inhibit voltage VINH. Also, as discussedabove, the plurality of global bit lines GB5(0)-GB5(x) are biased to theinhibit voltage VINH. Thus, for generating a voltage indicative of aresistive state of the resistive change element O01, a voltage on theword line W(1) transitions from the inhibit voltage VINH to the systemvoltage VDD and the voltages on the odd bit line Bo(0) and the globalbit line GB5(0) transition from the inhibit voltage VINH to a voltageindicative of a resistive state of the resistive change element O01.

The voltage transition of the voltage on the word line W(1) generallycorresponds with the voltage transition of the voltage on the topelectrode TE of the resistive change element O01 because the voltage onthe word line W(1) generally corresponds with the voltage on the topelectrode TE of the resistive change element O01. The voltage transitionof the voltage on the odd bit line Bo(0) generally corresponds with thevoltage transition of the voltage on the bottom electrode BE of theresistive change element O01 because the voltage on the odd bit lineBo(0) generally corresponds with the voltage on the bottom electrode BEof the resistive change element O01. The magnitude of the voltagetransition to place the top electrode TE of the resistive change elementO01 at the system voltage VDD for generating a voltage indicative of aresistive state of the resistive change element O01 is reduced becausethe voltage applied to the top electrode TE of the resistive changeelement O01 is not required to transition by the magnitude of the systemvoltage VDD. A voltage transition of the system voltage VDD minus theinhibit voltage VINH is required to place the top electrode at thesystem voltage VDD. For example, when the inhibit voltage VINH is VDD/2(half of the system voltage VDD) a voltage transition of VDD−VDD/2=VDD/2is required to place the top electrode at the system voltage VDD.Further, the number of voltage transitions for generating a voltageindicative of a resistive state of the resistive change element O01 isreduced because only voltages on the word line W(1), the global bit lineGB5(0), and the odd bit line Bo(0) are adjusted for generating a voltageindicative of a resistive state of the resistive change element O01. Itis noted that applying the inhibit voltage VINH to a top electrode, abottom electrode, or both a top electrode and a bottom electrode of aresistive change element limits a voltage applied across a resistivechange element to a voltage less than a voltage limit for disturbing aresistive state of a resistive change element while generating a voltageindicative of a resistive state of the resistive change element O01.

The voltage on the word line W(1) is driven from the inhibit voltageVINH to the system voltage VDD by changing the voltage supplied by theword line driver circuit 111 d from the inhibit voltage VINH to thesystem voltage VDD. The word line driver circuit 111 d changes fromsupplying the inhibit voltage VINH to the system voltage VDD based on asignal ITE1 supplied by control logic, such as a processor, acontroller, and a microcontroller. The write buffer circuit 150 does notsupply a voltage based on the write set signal WR0 and the write resetsignal WR1 supplied by control logic, such as a processor, a controller,and a microcontroller. The amount of current for a READ operation issunk from the bus line BLS by the current source 160. The amount ofcurrent for a READ operation is based on the amount of current thatwould flow through a resistor having an intermediate resistance andhaving the system voltage VDD applied to one terminal of the resistorand the inhibit voltage VINH applied to the other terminal of theresistor. The amount of current that would flow through a resistorhaving an intermediate resistance and having the system voltage VDDapplied to one terminal of the resistor and the inhibit voltage VINHapplied to the other terminal of the resistor can be approximated by thefollowing equation, I=(VDD−VINH)/Intermediate Resistance. For example,when the intermediate resistance=5.5MΩ, the system voltage VDD=2V, andthe inhibit voltage VINH=1V, the current source 160 is configured tosink an amount of current that can be approximated asI=(2V−1V)/5.5MΩ=0.18 μA. It is noted that, ignoring leakage currents,the amount of current for the READ operation flows through the resistivechange element O01, the odd bit line Bo(0), the global bit line GB5(0),and the bus line BLS to the current source 160.

The intermediate resistance sets a boundary for resistance values thatcorrespond with a low resistive state during READ operations andresistance values that correspond with a high resistive state duringREAD operations. The intermediate resistance is a design variable thatcan be selected by a circuit designer and the circuit designer typicallyselects an intermediate resistance greater than a model resistance for alow resistive state of a resistive change element and less than a modelresistance for a high resistive state of a resistive change element. Forexample, when a model resistance for a low resistive state of aresistive change element is 1MΩ and a model resistance for a highresistive state of a resistive change elements is 10MΩ, a circuitdesigner can select an intermediate resistance of 5.5MΩ so thatresistive change elements having a resistance less than approximately5.5MΩ are determined to have a low resistive state during READoperations and resistive change elements having a resistance greaterthan approximately 5.5MΩ are determined to have a high resistive stateduring READ operations. It is noted that the intermediate resistance isnot limited to a resistance at the exact midpoint between a modelresistance for a low resistive state of a resistive change element and amodel resistance for a high resistive state of a resistive changeelement, but rather the intermediate resistance can be closer the modelresistance for the low resistive state or the model resistance for thehigh resistive state.

FIG. 5D-1 shows a current IO01 flowing through the resistive changeelement O01 from the top electrode TE to the bottom electrode BE becausethe top electrode TE is at the system voltage VDD and the bottomelectrode BE is at a voltage indicative of a resistive state of theresistive change element O01. While, ignoring leakage currents, theamount of the current flowing through the resistive change element O01,the odd bit line Bo(0), the global bit line GB5(0), and the bus line BL5are the same amount of current (the amount of current of current for theREAD operation). Additionally, ignoring leakage currents, routingparasitics, and on resistance of the odd selection device No0, thevoltage VBo(0) on the odd bit line Bo(0), the voltage VGB5(0) on theglobal bit line GB5(0), and the voltage on the bus line BL5 aregenerally the same voltage and the voltage VBo(0) on the odd bit lineBo(0), the voltage VGB5(0) on the global bit line GB5(0), and thevoltage on the bus line BL5 are indicative of the resistive state of theresistive change element O01. It is noted that the voltage indicative ofa resistive state of the resistive change element O01 is discussed belowwith respect to the voltage VGB5(0) on the global bit line GB5(0).

The voltage VGB5(0) on the global bit line GB5(0), ignoring leakagecurrents, routing parasitics, and on resistance of the odd selectiondevice No0, can be approximated by subtracting the voltage drop acrossthe resistive change element O01 from the voltage VW(1) on the word lineW(1). The voltage drop across the resistive change element O01 can beapproximated using Ohm's Law. Thus, the voltage VGB5(0) on the globalbit line GB5(0) can be approximated by the following equationVGB5(0)=VW(1)−(IO01×RO01), where VW(1) is the voltage on the word lineW(1), the current IO01 is the current flowing through resistive changeelement O01, and RO01 is the resistance of the resistive change elementO01. As shown by this equation, the voltage VGB5(0) on the global bitline GB5(0) changes when the resistance of the resistive change elementO01 changes because the voltage VW(1) on the word line W(1) and thecurrent IO01 flowing through the resistive change element O01 aregenerally the same for READ operations. For example, when VW(1)=2 volts,IO01=1/5.5 microamps, and RO01=5.5MΩ, the voltage VGB5(0)=2V−(1/5.5μA×5.5MΩ)=1V. For example, when VW(1)=2 volts, IO01=1/5.5 microamps, andRO01=1MΩ, the voltage VGB5(0)=2V−(1/5.5 μA×1MΩ)=1.82V. For example, whenVW(1)=2 volts, IO01=1/5.5 microamps, and RO01=10MΩ, the voltageVGB5(0)=2V−(1/5.5 μA×10 MΩ)=0.182V.

FIG. 5D-1 also shows leakage currents flowing through the resistivechange elements O00, O0 y in electrical communication with the odd bitline Bo(0) and leakage currents flowing through the resistive changeelements E01, Ex1-Ox1 in electrical communication with the word lineW(1). The leakage currents are shown using dashed lines in FIG. 5D-1.Leakage currents flow through the resistive change elements O00, O0 ybecause the bottom electrodes of the resistive change elements O00, O0 yare at a voltage indicative of a resistive state of the resistive changeelement O01 and the top electrodes of the resistive change elements O00,O0 y are the inhibit voltage VINH. Leakage currents flow throughresistive change elements E01, Ex1-Ox1 because the bottom electrodes ofthe resistive change elements E01, Ex1-Ox1 are at the inhibit voltageVINH and the top electrodes of the resistive change elements E01,Ex1-Ox1 are at the system voltage VDD. It is noted that leakage currentsmay flow through resistive change elements other than the resistivechange elements in electrical communication with the odd bit line Bo(0)and the resistive change elements in electrical communication with theword line W(1) because voltages on other lines may be impacted bygenerating a voltage indicative of a resistive state of the resistivechange element O01. It is also noted that leakage currents do notprevent the READ operation of the resistive change element O01 when theleakage currents are much less than the amount of the current IO01. Itis further noted that the voltage differences across the resistivechange elements that cause the leakage currents do not disturb theresistive states of the resistive change elements because the voltagedifferences are less than a voltage limit for disturbing a resistivestate of a resistive change element.

It is additionally noted that when the voltage VBo(0) on the odd bitline Bo(0) is less than the inhibit voltage VINH and the word linesW(0), W(y) in electrical communication with the other resistive changeelements O00, O0 y on the odd bit line Bo(0) are driven to the inhibitvoltage VINH, leakage currents flow into the odd bit line Bo(0) throughthe other resistive change elements O00, O0 y and pull up the voltageVBo(0) on the odd bit line Bo(0). It is also noted that when the voltageVBo(0) on the odd bit line Bo(0) is greater than the inhibit voltageVINH and the word lines W(0), W(y) in electrical communication with theother resistive change elements O00, O0 y on the odd bit line Bo(0) aredriven to the inhibit voltage VINH, leakage currents flow from the oddbit line Bo(0) through the other resistive change elements O00, O0 y andpull down the voltage VBo(0) on the bit line Bo(0). It is further notedthat when the voltage VBo(0) on the odd bit line Bo(0) is pulled up byleakage currents flowing into the odd bit line Bo(0) and when thevoltage VBo(0) on the odd bit line Bo(0) is pulled down by leakagecurrents flowing from the odd bit line Bo(0), the number of the wordlines W(0), W(y) should be small enough to allow a margin to determine aresistive state of the resistive change element O01.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 412 of the flow chart 400, bydetermining the resistive state of the resistive change element O01based on the voltage VGB5(0) on the global bit line GB5(0). Theresistive state of the resistive change element O01 is determined bycomparing the voltage VGB5(0) on with global bit line GB5(0) with theinhibit voltage VINH on the reference line RLS. As discussed above, thevoltage VGB5(0) on the global bit line GB5(0) is indicative of theresistive state of the resistive change element O01. For READ operationsthe inhibit voltage VINH is indicative of the intermediate resistancebecause the inhibit voltage VINH is equal to the system voltage VDDminus a voltage calculated by multiplying the amount of current for aREAD operation and the intermediate resistance of 5.5MΩ. For example,when the system voltage VDD=2V, the inhibit voltage VINH=1V, the amountof current for READ operations=1/5.5 μA, and the intermediateresistance=5.5MΩ, VINH=2V−(1/5.5 μA×5.5MΩ)=1V. When the voltage VGB5(0)on the global bit line GB5(0) is greater than the inhibit voltage (i.e.the voltage VGB5(0) on the global bit line GB5(0)>VINH) the resistanceof the resistive change element O01 is less than the intermediateresistance (i.e. RO01<intermediate resistance, where RO01 is theresistance of the resistive change element O01) and the resistive stateof the resistive change element O01 is determined to be a low resistivestate. When the voltage VGB5(0) on the global bit line GB5(0) is lessthan the inhibit voltage VINH (i.e. the voltage VGB5(0) on the globalbit line GB5(0)<VINH) the resistance of the resistive change element O01is greater than the intermediate resistance (i.e. RO01>intermediateresistance, where RO01 is the resistance of the resistive change elementO01) and the resistive state of resistive change element O01 isdetermined to be a high resistive state.

As shown in FIG. 5D-2, the first input device 510 receives the voltageVGB5(0) on the global bit line GB5(0), the inhibit voltage VINH from apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH, the initialization signal INIT, andthe complementary initialization signal INITB, and the second inputdevice 520 receives the inhibit voltage VINH on the reference line RL5,the inhibit voltage VINH from a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH, theinitialization signal INIT, and the complementary initialization signalINITB. When the initialization signal INIT has a low level and thecomplementary initialization signal INITB has a high level, the firstinput device 510 supplies the voltage VGBS(0) on the global bit lineGB5(0) to the sense amplifier 550 and the second input device 520supplies the inhibit voltage VINH on the reference line RL5 to the senseamplifier 550. When the initialization signal INIT has a high level andthe complementary initialization signal INITB has a low level, the firstinput device 510 supplies the inhibit voltage VINH from a power supply,a voltage source, a driver circuit, or other device that supplies theinhibit voltage VINH to the sense amplifier 550 and the second inputdevice 520 supplies the inhibit voltage VINH from a power supply, avoltage source, a driver circuit, or other device that supplies theinhibit voltage VINH to the sense amplifier 550.

When the initialization signal INIT has a low level and thecomplementary initialization signal INITB has a high level the senseamplifier 550 receives the voltage VGBS(0) on the global bit line GB5(0)and the inhibit voltage VINH on the reference line RLS. The senseamplifier 550 determines the resistive state of the resistive changeelement O01 by comparing the inhibit voltage VINH on the reference lineRL5 with the voltage VGB5(0) on the global bit line GB5(0). The senseamplifier 550 outputs signals indicative of the resistive state of theresistive change element O01 on two outputs. When the voltage VGB5(0) onthe global bit line GB5(0) is greater than the inhibit voltage VINH, thesense amplifier 550 outputs signals indicating the resistive changeelement O01 has a low resistive state. When the voltage VGB5(0) on theglobal bit line GB5(0) is less than the inhibit voltage VINH, the senseamplifier 550 outputs signals indicating the resistive change elementO01 has a high resistive state. The operation of the sense amplifier 550when the sense amplifier 550 is a second sense amplifier 600 isdiscussed in greater detail with respect to the simplified schematicdiagram of the second sense amplifier 600 shown in FIG. 6 and theexemplary voltage waveforms for describing operation of the second senseamplifier 600 for READ operations of resistive change element 001. Theoperation of the sense amplifier 550 when the sense amplifier 550 is athird sense amplifier 700 is discussed in greater detail with respect tothe simplified schematic diagram of the third sense amplifier 700 shownin FIG. 7 and the exemplary voltage waveforms for describing operationof the third sense amplifier 700 for READ operations of resistive changeelement O01. It is noted that providing the inhibit voltage VINH on thereference line RL5 to the sense amplifier 550 can increase the accuracyof determining the resistive state of the resistive change element O01because the inhibit voltage VINH on the reference line RL5 and thevoltage on the global bit line GB5(0) are subject to similar conditions.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 414 of the flow chart 400, byrestoring neutral voltage conditions for resistive change elementsimpacted by generating a voltage indicative of a resistive state of theresistive change element O01. Neutral voltage conditions are restoredfor resistive change elements impacted by generating a voltageindicative of a resistive state of the resistive change element O01 byfloating the plurality of odd bit lines Bo(0)-Bo(x) and applying theinhibit voltage VINH to the word line W(1). The plurality of even bitlines Be(0)-Be(x) are already floating because the plurality of evenselection devices Ne0-Nex are turned off. The inhibit voltage VINH isalready applied to the word lines W(0), W(y) because the word linedriver circuits 110 d, 11 yd are already supplying the inhibit voltageVINH. The plurality of odd bit lines Bo(0)-Bo(x) are floated bydisconnecting the plurality of odd bit lines Bo(0)-Bo(x) from theplurality of global bit lines GB5(0)-GB5(x) by turning off the pluralityof odd selection devices No0-Nox. The plurality of odd selection devicesNo0-Nox are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELo having a lowlevel. The inhibit voltage VINH is applied to the word line W(1) by theword line driver circuit 111 d driving the voltage on the word line W(1)to the inhibit voltage VINH. The word line driver circuit 111 d suppliesthe inhibit voltage VINH based on a signal ITE1 supplied by controllogic, such as a processor, a controller, and a microcontroller. Thus,the inhibit voltage VINH is applied to the plurality of word linesW(0)-W(y) with the plurality of even bit lines Be(0)-Be(x) and theplurality of odd bit lines Bo(0)-Bo(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00-Oxy.

The READ operation of the resistive change element O01 proceeds, assimilarly discussed above in step 416 of the flow chart 400, by biasingglobal bit lines impacted by generating a voltage indicative of aresistive state of the resistive change element O01. Global bit linesimpacted by generating a voltage indicative of a resistive state of theresistive change element O01 are biased to the inhibit voltage VINH byfloating the plurality of global bit lines GB5(0)-GB5(x) and applyingthe inhibit voltage VINH to global bit lines having even column numbers.The plurality of global bit lines GB5(0)-GB5(x) are floated bydisconnecting the plurality of global bit lines GB5(0)-GB5(x) from theplurality of odd bit lines Bo(0)-Bo(x) and disconnecting the global bitline GB5(0) from the bus line BL5. The plurality of global bit linesGB5(0)-GB5(x) are already disconnected from the plurality of even bitlines Be(0)-Be(x) because the plurality of even selection devicesNe0-Nex are turned off. The global bit lines other than global bit lineGB5(0) are already disconnected from the bus line BL5 because the PMOStransistors in the first plurality of PMOS transistors 540 g-54 xg otherthan PMOS transistor 540 g are turned off. The plurality of global bitlines GB5(0)-GB5(x) may be disconnected from the plurality of odd bitlines Bo(0)-Bo(x) as part of restoring neutral voltage conditions forresistive change elements impacted by generating a voltage indicative ofa resistive state of the resistive change element O01 as discussedabove. The global bit line GB5(0) is disconnected from the bus line BL5by turning off the PMOS transistor 540 g. The PMOS transistor 540 g isturned off by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal YD0 having a high level. The inhibitvoltage VINH is already applied to the global bit lines having oddcolumn numbers because the global bit lines having odd column numbersare in electrical communication with a power supply, a voltage source, adriver circuit, or other device that supplies the inhibit voltage VINHbecause the NMOS transistors 13 xk are turned on. The inhibit voltageVINH is applied to the global bit lines having even column numbers byelectrically connecting the global bit lines having even column numbersto a power supply, a voltage source, a driver circuit, or other devicethat supplies the inhibit voltage VINH by turning on the NMOStransistors 130 k. The NMOS transistors 130 k in electricalcommunication with the global bit lines having even column numbers areturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level. It isnoted that control logic, such as a processor, a controller, and amicrocontroller, supplying a signal YD0 having a high level also turnsoff the PMOS transistor 540 r in the global bit line connection circuit540.

Referring now to FIGS. 5E-1 and 5E-2, a simplified schematic diagram ofthe exemplary implementation of the second exemplary architectureshowing current flow through the resistive change element array 100during a READ operation of resistive change element O01 when resistivechange element O01 has a high resistive state is illustrated. A READoperation of the resistive change element O01 when resistive changeelement O01 has a high resistive state is performed in the same manneras a READ operation of the resistive change element O01 when resistivechange element O01 has a low resistive as discussed above with respectto FIGS. 5D-1 and 5D-2. However, a voltage indicative of a resistivestate of resistive change element O01 when resistive change element O01has a high resistive state differs from a voltage indicative of aresistive state of resistive change element O01 when resistive changeelement O01 has a low resistive state. Thus, current flow through theresistive change element array 100 during a READ operation of theresistive change element O01 when resistive change element O01 has ahigh resistive state may differ from current flow through the resistivechange element array 100 during a READ operation of the resistive changeelement O01 when resistive change element O01 has a low resistive state.

FIG. 5E-1 shows a current 1001 flowing through the resistive changeelement O01 from the top electrode TE to the bottom electrode BE becausethe top electrode TE is at the system voltage VDD and the bottomelectrode BE is at a voltage indicative of a resistive state of theresistive change element O01. FIG. 5E-1 also shows leakage currentsflowing through the resistive change elements O00, O0 y in electricalcommunication with the odd bit line Bo(0) and leakage currents flowingthrough the resistive change elements E01, Ex1-Ox1 in electricalcommunication with the word line W(1). The leakage currents are shownusing dashed lines in FIG. 5E-1. Leakage currents flow through theresistive change elements O00, O0 y because the bottom electrodes of theresistive change elements O00, O0 y are at a voltage indicative of aresistive state of the resistive change element O01 and the topelectrodes of the resistive change elements O00, O0 y are the inhibitvoltage VINH. Leakage currents flow through resistive change elementsE01, Ex1-Ox1 because the bottom electrodes of the resistive changeelements E01, Ex1-Ox1 are at the inhibit voltage VINH and the topelectrodes of the resistive change elements E01, Ex1-Ox1 are at thesystem voltage VDD. It is noted that leakage currents may flow throughresistive change elements other than the resistive change elements inelectrical communication with the odd bit line Bo(0) and the resistivechange elements in electrical communication with the word line W(1)because voltages on other lines may be impacted by generating a voltageindicative of a resistive state of the resistive change element O01. Itis also noted that leakage currents do not prevent the READ operation ofthe resistive change element 001 when the leakage currents are much lessthan the amount of the current IO01. It is further noted that thevoltage differences across the resistive change elements that cause theleakage currents do not disturb the resistive states of the resistivechange elements because the voltage differences are less than a voltagelimit for disturbing a resistive state of a resistive change element.

SET VERIFY operations of resistive change elements in the exemplaryimplementation of the second exemplary architecture can be performed ina similar manner to READ operations of resistive change element O01discussed above, but with the current source 160 set to sink an amountof current for a SET VERIFY operation. The amount of current for a SETVERIFY operation is based on the amount of current that would flowthrough a resistor having a low resistance and having the system voltageVDD applied to one terminal of the resistor and the inhibit voltage VINHapplied to the other terminal of the resistor. The amount of currentthat would flow through a resistor having a low resistance and havingthe system voltage VDD applied to one terminal of the resistor and theinhibit voltage VINH applied to the other terminal of the resistor canbe approximated by the following equation, I=(VDD−VINH)/Low Resistance.For example, when the low resistance is 2MΩ, the system voltage VDD is2V, and the inhibit voltage VINH is 1V, the current source 160 isconfigured to sink an amount of current for a SET VERIFY operation thatcan be approximated as I=(2V−1V)/2MΩ=0.5 μA.

The low resistance sets an upper boundary for resistance values thatcorrespond with a low resistive state during SET VERIFY operations. Thelow resistance is a design variable that can be selected by a circuitdesigner and the circuit designer typically selects a low resistancegreater than a model resistance for a low resistive state of a resistivechange element so that resistive change elements can have resistancesgreater than the model resistance for the low resistive state and bedetermined to have a low resistive state during SET VERIFY operations.For example, when a model resistance for a low resistive state of aresistive change element is 1MΩ, a circuit designer can select a lowresistance of 2MΩ so that resistive change elements having a resistanceless than approximately 2MΩ are determined to have a low resistive stateduring SET VERIFY operations. It is noted that the circuit designertypically selects a low resistance greater than a model resistance for alow resistive state of a resistive change element and less than anintermediate resistance for READ operations.

RESET VERIFY operations of resistive change elements in the exemplaryimplementation of the second exemplary architecture can be performed ina similar manner to READ operations of resistive change element O01discussed above, but with the current source 160 set to sink an amountof current for a RESET VERIFY operation. The amount of current for aRESET VERIFY operation is based on the amount of current that would flowthrough a resistor having a high resistance and having the systemvoltage VDD applied to one terminal of the resistor and the inhibitvoltage VINH applied to the other terminal of the resistor. The amountof current that would flow through a resistor having a high resistanceand having the system voltage VDD applied to one terminal of theresistor and the inhibit voltage VINH applied to the other terminal ofthe resistor can be approximated by the following equation,I=(VDD−VINH)/High Resistance. For example, when the high resistance is9MΩ, the system voltage VDD is 2V, and the inhibit voltage VINH is 1V,the current source 160 is configured to sink an amount of current for aRESET VERIFY operation that can be approximated as I=(2V−1V)/9MΩ=0.11μA.

The high resistance sets an upper boundary for resistance values thatcorrespond with a high resistive state during RESET VERIFY operations.The high resistance is a design variable that can be selected by acircuit designer and the circuit designer typically selects a highresistance less than a model resistance for a high resistive state of aresistive change element so that resistive change elements can haveresistances less than the model resistance for the high resistive stateand be determined to have a high resistive state during RESET VERIFYoperations. For example, when a model resistance for a high resistivestate of a resistive change element is 10MΩ, a circuit designer canselect a high resistance of 9MΩ so that resistive change elements havinga resistance greater than approximately 9MΩ are determined to have ahigh resistive state during RESET VERIFY operations. It is noted thatthe circuit designer typically selects a high resistance less than amodel resistance for a high resistive state of a resistive changeelement and greater than an intermediate resistance for READ operations.

Referring now to FIG. 6, the second sense amplifier 600 receives avoltage V510 provided by the first input device 510, a voltage V520provided by the second input device 520, an initialization signal INIT,a complementary initialization signal INITB, a first power on signalPONB, a second power on signal NON, a sense amplifier enable signalSAEN, and a bias current signal BIAS, and outputs a voltage VoutB and avoltage Vout. The second sense amplifier 600 includes a first voltageswing limiter 610, a second voltage swing limiter 620, a first loaddevice 630, a second load device 640, a current source 650, a firstcoupling canceller 680, a second coupling canceller 690, a power controldevice 660, and a latch device 670. The first voltage swing limiter 610includes a NMOS transistor 611 having a drain terminal, a gate terminal,and a source terminal and a PMOS transistor 612 having a drain terminal,a gate terminal, and a source terminal. The drain terminal of the NMOStransistor 611 is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies thesystem voltage VDD. The gate terminal of the NMOS transistor 611 is inelectrical communication with the first load device 630 and the gateterminal of the PMOS transistor 612. The source terminal of the NMOStransistor 611 is in electrical communication with the second loaddevice 640 and the source terminal of the PMOS transistor 612. The drainterminal of the PMOS transistor 612 is in electrical communication witha power supply, a voltage source, a driver circuit, or other device thatsupplies 0 volts or ground. The gate terminal of the PMOS transistor 612is in electrical communication with the first load device 630 and thegate terminal of the NMOS transistor 611. The source terminal of thePMOS transistor 612 is in electrical communication with the second loaddevice 640 and the source terminal of the NMOS transistor 611.

The second voltage swing limiter 620 includes a NMOS transistor 621having a drain terminal, a gate terminal, and a source terminal and aPMOS transistor 622 having a drain terminal, a gate terminal, and asource terminal. The drain terminal of the NMOS transistor 621 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies the system voltage VDD. The gateterminal of the NMOS transistor 621 is in electrical communication withthe second load device 640 and the gate terminal of the PMOS transistor622. The source terminal of the NMOS transistor 621 is in electricalcommunication with the first load device 630 and the source terminal ofthe PMOS transistor 622. The drain terminal of the PMOS transistor 622is in electrical communication with a power supply, a voltage source, adriver circuit, or other device that supplies 0 volts or ground. Thegate terminal of the PMOS transistor 622 is in electrical communicationwith the second load device 640 and the gate terminal of the NMOStransistor 621. The source terminal of the PMOS transistor 622 is inelectrical communication with the first load device 630 and the sourceterminal of the NMOS transistor 621.

The first load device 630 includes a first NMOS transistor 631 having adrain terminal, a gate terminal, and a source terminal, a first PMOStransistor 632 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 633 having a drain terminal, a gateterminal, and a source terminal, a second PMOS transistor 634 having adrain terminal, a gate terminal, and a source terminal, a firstcapacitor connected PMOS transistor 635 having a drain terminal, a gateterminal, and a source terminal, and a second capacitor connected PMOStransistor 636 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 631 is inelectrical communication with the first coupling canceller 680, thesecond voltage swing limiter 620, the power control device 660, thefirst voltage swing limiter 610, the second load device 640, the drainterminal of the first PMOS transistor 632, the drain terminal of thesecond PMOS transistor 634, and the source terminal of the second NMOStransistor 633. The gate terminal of the first NMOS transistor 631 is inelectrical communication with the first input device 510 and the secondcoupling canceller 690. The source terminal of the first NMOS transistor631 is in electrical communication with the current source 650 and thesecond load device 640. The drain terminal of the first PMOS transistor632 is in electrical communication with the drain terminal of the secondPMOS transistor 634, the source terminal of the second NMOS transistor633, the second load device 640, the first voltage swing limiter 610,the power control device 660, the second voltage swing limiter 620, thefirst coupling canceller 680, and the drain terminal of the first NMOStransistor 631. The gate terminal of the first PMOS transistor 632 is inelectrical communication with the source terminal of the second PMOStransistor 634, the drain terminal of the second NMOS transistor 633,the gate terminal of first capacitor connected PMOS transistor 635, andthe gate terminal of the second capacitor connected PMOS transistor 636.The source terminal of the first PMOS transistor 632 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the system voltage VDD. The drain terminalof the second NMOS transistor 633 is in electrical communication withthe source terminal of the second PMOS transistor 634, the gate terminalof the first PMOS transistor 632, the gate terminal of the firstcapacitor connected PMOS transistor 635, and the gate terminal of thesecond capacitor connected PMOS transistor 636. The gate terminal of thesecond NMOS transistor 633 is in electrical communication with controllogic, such as a processor, a controller, and a microcontroller, toreceive the initialization signal INIT. The source terminal of thesecond NMOS transistor 633 is in electrical communication with the drainterminal of the second PMOS transistor 634, the drain terminal of thefirst PMOS transistor 632, the second load device 640, the first voltageswing limiter 610, the power control device 660, the second voltageswing limiter 620, the first coupling canceller 680, and the drainterminal of the first NMOS transistor 631. The drain terminal of thesecond PMOS transistor 634 is in electrical communication with thesource terminal of the second NMOS transistor 633, the drain terminal ofthe first PMOS transistor 632, the second load device 640 the firstvoltage swing limiter 610, the power control device 660, the secondvoltage swing limiter 620, the first coupling canceller 680, and thedrain terminal of the first NMOS transistor 631. The gate terminal ofthe second PMOS transistor 634 is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive the complementary initialization signal INITB. The sourceterminal of the second PMOS transistor 634 is in electricalcommunication with the gate terminal of the first PMOS transistor 632,the drain terminal of the second NMOS transistor 633, the gate terminalof the first capacitor connected PMOS transistor 635, and the gateterminal of the second capacitor connected PMOS transistor 636. Thedrain terminal and the source terminal of the first capacitor connectedPMOS transistor 635 are in electrical communication and the drainterminal and the source terminal are in electrical communication withthe second load device 640. The gate terminal of the first capacitorconnected PMOS transistor 635 is in electrical communication with thedrain terminal of the second NMOS transistor 633, the source terminal ofthe second PMOS transistor 634, the gate terminal of the first PMOStransistor 632, and the gate terminal of the second capacitor connectedPMOS transistor 636. The drain terminal and the source terminal of thesecond capacitor connected PMOS transistor 636 are in electricalcommunication and the drain terminal and the source terminal are inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies the system voltage VDD. The gateterminal of the second capacitor connected PMOS transistor 636 is inelectrical communication with the gate terminal of the first PMOStransistor 632, the source terminal of the second PMOS transistor 634,the drain terminal of the second NMOS transistor 633, and the gateterminal of the first capacitor connected PMOS transistor 635.

The second load device 640 includes a first NMOS transistor 641 having adrain terminal, a gate terminal, and a source terminal, a first PMOStransistor 642 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 643 having a drain terminal, a gateterminal, and a source terminal, a second PMOS transistor 644 having adrain terminal, a gate terminal, and a source terminal, a firstcapacitor connected PMOS transistor 645 having a drain terminal, a gateterminal, and a source terminal, and a second capacitor connected PMOStransistor 646 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 641 is inelectrical communication with the second coupling canceller 690, thefirst voltage swing limiter 610, the power control device 660, thesecond voltage swing limiter 620, the first load device 630, the drainterminal of the first PMOS transistor 642, the drain terminal of thesecond PMOS transistor 644, and the source terminal of the second NMOStransistor 643. The gate terminal of the first NMOS transistor 641 is inelectrical communication with the second input device 520. The sourceterminal of the first NMOS transistor 641 is in electrical communicationwith the current source 650 and the first load device 630. The drainterminal of the first PMOS transistor 642 is in electrical communicationwith the drain terminal of the second PMOS transistor 644, the sourceterminal of the second NMOS transistor 643, the first load device 630,the second voltage swing limiter 620, the power control device 660, thefirst voltage swing limiter 610, the second coupling canceller 690, andthe drain terminal of the first NMOS transistor 641. The gate terminalof the first PMOS transistor 642 is in electrical communication with thesource terminal of the second PMOS transistor 644, the drain terminal ofthe second NMOS transistor 643, the gate terminal of the first capacitorconnected PMOS transistor 645, and the gate terminal of the secondcapacitor connected PMOS transistor 646. The source terminal of thefirst PMOS transistor 642 is in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The drain terminal of the second NMOStransistor 643 is in electrical communication with the source terminalof the second PMOS transistor 644, the gate terminal of the first PMOStransistor 642, the gate terminal of the first capacitor connected PMOStransistor 645, and the gate terminal of the second capacitor connectedPMOS transistor 646. The gate terminal of the second NMOS transistor 643is in electrical communication with control logic, such as a processor,a controller, and a microcontroller, to receive the initializationsignal INIT. The source terminal of the second NMOS transistor 643 is inelectrical communication with the drain terminal of the second PMOStransistor 644, the drain terminal of the first PMOS transistor 642, thefirst load device 630, the second voltage swing limiter 620, the powercontrol device 660, the first voltage swing limiter 610, the secondcoupling canceller 690, and the drain terminal of the first NMOStransistor 641. The drain terminal of the second PMOS transistor 644 isin electrical communication with the source terminal of the second NMOStransistor 643, the drain terminal of the first PMOS transistor 642, thefirst load device 630, the second voltage swing limiter 620, the powercontrol device 660, the first voltage swing limiter 610, the secondcoupling canceller 690, and the drain terminal of the first NMOStransistor 641. The gate terminal of the second PMOS transistor 644 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the complementaryinitialization signal INITB. The source terminal of the second PMOStransistor 644 is in electrical communication with the gate terminal ofthe first PMOS transistor 642, the drain terminal of the second NMOStransistor 643, the gate terminal of the first capacitor connected PMOStransistor 645, and the gate terminal of the second capacitor connectedPMOS transistor 646. The drain terminal and the source terminal of thefirst capacitor connected PMOS transistor 645 are in electricalcommunication and the drain terminal and the source terminal are inelectrical communication with the first load device 630. The gateterminal of the first capacitor connected PMOS transistor 645 is inelectrical communication with the drain terminal of the second NMOStransistor 643, the source terminal of the second PMOS transistor 644,the gate terminal of the first PMOS transistor 642, and the gateterminal of the second capacitor connected PMOS transistor 646. Thedrain terminal and the source terminal of the second capacitor connectedPMOS transistor 646 are in electrical communication and the drainterminal and the source terminal are in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The gate terminal of the secondcapacitor connected PMOS transistor 646 is in electrical communicationwith the gate terminal of the first PMOS transistor 642, the sourceterminal of the second PMOS transistor 644, the drain terminal of thesecond NMOS transistor 643, and the gate terminal of the first capacitorconnected PMOS transistor 645.

The current source 650 includes a first NMOS transistor 652 have a drainterminal, a gate terminal, and a source terminal and a second NMOStransistor 654 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 652 is inelectrical communication with the first load device 630 and the secondload device 640. The gate terminal of the first NMOS transistor 652 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the sense amplifier enablesignal SAEN. The source terminal of the first NMOS transistor 652 is inelectrical communication with the drain terminal of the second NMOStransistor 654. The drain terminal of the second NMOS transistor 654 isin electrical communication with the source terminal of the first NMOStransistor 652. The gate terminal of the second NMOS transistor 654 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the bias current signalBIAS. The source terminal of the second NMOS transistor 654 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground.

The first coupling canceller 680 includes a capacitor connected NMOStransistor 681 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal and the source terminal of the capacitorconnected NMOS transistor 681 are in electrical communication and thedrain terminal and the source terminal are in electrical communicationwith the second input device 520 and the second load device 640. Thegate terminal of the first capacitor connected NMOS transistor 681 is inelectrical communication with the first load device 630. The secondcoupling canceller 690 includes a capacitor connected NMOS transistor691 having a drain terminal, a gate terminal, and a source terminal. Thedrain terminal and the source terminal of the capacitor connected NMOStransistor 691 are in electrical communication and the drain terminaland the source terminal are in electrical communication with the firstinput device 510 and the first load device 630. The gate terminal of thecapacitor connected NMOS transistor 691 is in electrical communicationwith the second load device 640.

The power control device 660 includes a PMOS transistor 662 having adrain terminal, a gate terminal, and a source terminal, a first NMOStransistor 664 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 667 having a drain terminal, a gateterminal, and a source terminal, and a third NMOS transistor 668 havinga drain terminal, a gate terminal, and a source terminal. The drainterminal of the PMOS transistor 662 is in electrical communication withthe latch device 670. The gate terminal of the PMOS transistor 662 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the first power on signalPONB. The source terminal of the PMOS transistor 662 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the system voltage VDD. The drain terminalof the first NMOS transistor 664 is in electrical communication with thelatch device 670. The gate terminal of the first NMOS transistor 664 isin electrical communication control logic, such as a processor, acontroller, and a microcontroller, to receive the second power on signalNON. The source terminal of the first NMOS transistor 664 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The drainterminal of the second NMOS transistor 667 is in electricalcommunication with the latch device 670. The gate terminal of the secondNMOS transistor 667 is in electrical communication with control logic,such as a processor, a controller, and a microcontroller, to receive thefirst power on signal PONB. The source terminal of the second NMOStransistor 667 is in electrical communication with the first load device630. The drain terminal of the third NMOS transistor 668 is inelectrical communication with the second load device 640. The gateterminal of the third NMOS transistor 668 is in electrical communicationwith control logic, such as a processor, a controller, and amicrocontroller, to receive the first power on signal PONB. The sourceterminal of the third NMOS transistor 668 is in electrical communicationwith the latch device 670. Alternatively, each of the second NMOStransistor 667 and the third NMOS transistor 668 may be replaced with aNMOS transistor and a PMOS transistor in electrical communication inparallel, with each of the NMOS transistors having a drain terminal, agate terminal, and a source terminal, each of the PMOS transistorshaving a drain terminal, a gate terminal, and a source terminal, thegate terminals of both NMOS transistors in electrical communication witha circuit to receive a signal to turn on and turn off both NMOStransistors, the gate terminals of both PMOS transistors in electricalcommunication with a circuit to receive a signal to turn on and turn offboth PMOS transistors, and the signals being coordinated such that bothNMOS transistors and both PMOS transistors are turned on and turned offat generally the same time.

The latch device 670 includes a first PMOS transistor 672 having a drainterminal, a gate terminal, and a source terminal, a first NMOStransistor 674 having a drain terminal, a gate terminal, and a sourceterminal, a second PMOS transistor 676 having a drain terminal, a gateterminal, and a source terminal, and a second NMOS transistor 678 havinga drain terminal, a gate terminal, and a source terminal. The drainterminal of the first PMOS transistor 672 is in electrical communicationwith the gate terminal of the second PMOS transistor 676, the gateterminal of the second NMOS transistor 678, the power control device660, and the drain terminal of the first NMOS transistor 674. The gateterminal of the first PMOS transistor 672 is in electrical communicationwith the drain terminal of the second PMOS transistor 676, the drainterminal of the second NMOS transistor 678, the power control device660, and the gate terminal of the first NMOS transistor 674. The sourceterminal of the first PMOS transistor 672 is in electrical communicationwith the power control device 660 and the source terminal of the secondPMOS transistor 676. The drain terminal of the first NMOS transistor 674is in electrical communication with the power control device 660, thegate terminal of the second PMOS transistor 676, the gate terminal ofthe second NMOS transistor 678, and the drain terminal of the first PMOStransistor 672. The gate terminal of the first NMOS transistor 674 is inelectrical communication with the drain terminal of the second PMOStransistor 676, the drain terminal of the second NMOS transistor 678,the power control device 660, and the gate terminal of the first PMOStransistor 672. The source terminal of the first NMOS transistor 674 isin electrical communication with the power control device 660 and thesource terminal of the second NMOS transistor 678. The drain terminal ofthe second PMOS transistor 676 is in electrical communication with thepower control device 660, the gate terminal of the first PMOS transistor672, the gate terminal of the first NMOS transistor 674, and the drainterminal of the second NMOS transistor 678. The gate terminal of thesecond PMOS transistor 676 is in electrical communication with the drainterminal of the first PMOS transistor 672, the drain terminal of thefirst NMOS transistor 674, the power control device 660, and the gateterminal of the second NMOS transistor 678. The source terminal of thesecond PMOS transistor 676 is in electrical communication with the powercontrol device 660 and the source terminal of the first PMOS transistor672. The drain terminal of the second NMOS transistor 678 is inelectrical communication with the power control device 660, the gateterminal of the first PMOS transistor 672, the gate terminal of thefirst NMOS transistor 674, and the drain terminal of the second PMOStransistor 676. The gate terminal of the second NMOS transistor 678 isin electrical communication with the drain terminal of the first PMOStransistor 672, the drain terminal of the first NMOS transistor 674, thepower control device 660, and the gate terminal of the second PMOStransistor 676. The source terminal of the second NMOS transistor 678 isin electrical communication with the power control device 660 and thesource terminal of the first NMOS transistor 674.

Referring to the simplified schematic diagram of the second senseamplifier 600 shown in FIG. 6, the first load device 630 receives thevoltage V510 provided by the first input device 510, the initializationsignal INIT, and the complementary initialization signal INITB. Thesecond load device 640 receives the voltage V520 provided by the secondinput device 520, the initialization signal INIT, and the complementaryinitialization signal INITB. The current source 650 receives the senseamplifier enable signal SAEN and the bias current signal BIAS. The powercontrol device 660 receives the first power on signal PONB and thesecond power on signal NON. Control logic, such as a processor, acontroller, and a microcontroller, supplies the initialization signalINIT, the complementary initialization signal INITB, the sense amplifierenable signal SAEN, the bias current signal BIAS, the first power onsignal PONB, and the second power on signal NON to the second senseamplifier 600. Exemplary voltage waveforms for the initialization signalINIT, the complementary initialization signal INITB, the sense amplifierenable signal SAEN, the first power on signal PONB, and the second poweron signal NON for describing operation of the second sense amplifier 600for READ operations of resistive change element O01 are shown in FIG.2B. Additionally, although an exemplary voltage waveform for the biascurrent signal BIAS is not shown in FIG. 2B, the control logic suppliesthe bias current signal BIAS. The control logic supplies the senseamplifier enable signal SAEN to enable and disable the current source650 and the bias current signal BIAS to set the amount of current sunkby the current source 650. Also, exemplary voltage waveforms for thesignal YD0, the signal SSELo, the signal KEEPe, the voltage VW(1) on theword line W(1), the voltage on the reference line RL5 labeled as thevoltage REF, and the voltage VGB5(0) on the global bit line GB5(0)labeled as the voltage VGB for describing operation of the second senseamplifier 600 for READ operations of resistive change element O01 areshown in FIG. 2B. Further, FIG. 2B shows two exemplary voltage waveformsfor the voltage VGB, a voltage waveform for when the resistive changeelement O01 has a low resistive state and a voltage waveform for whenthe resistive change element O01 has a high resistive state.

The second sense amplifier 600 is in an initializing configuration whenthe initialization signal INIT has a high level and the complementaryinitialization signal INITB has a low level and the second senseamplifier 600 is in a comparing configuration when the initializationsignal INIT has a low level and the complementary initialization signalINITB has a high level. When the second sense amplifier 600 is in aninitializing configuration the first PMOS transistor 632 of the firstload device 630 is electrically connected to function as a diode and thefirst PMOS transistor 642 of the second load device 640 is electricallyconnected to function as a diode. When the second sense amplifier 600 isin a comparing configuration the first PMOS transistor 632 iselectrically connected to function as a resistor and the first PMOStransistor 642 is electrically connected to function as a resistor withthe operating points of the first PMOS transistor 632 and the secondPMOS transistor 642 set to compensate for performance differencesbetween the first load device 630 and the second load device 640 bykeeping the gate voltage of the first PMOS transistor 632 at a biasvoltage VB632 and the gate voltage of the first PMOS transistor 642 at abias voltage VB642. Additionally, when the initialization signal INIThas a high level and the complementary initialization signal INITB has alow level the first input device 510 provides the inhibit voltage VINHto the first load device 630 and the second input device 520 providesthe inhibit voltage VINH to the second load device 640. Further, whenthe initialization signal INIT has a low level and the complementaryinitialization signal INITB has a high level the first input device 510provides the voltage VGB5(0) on the global bit line GB5(0) to the firstload device 630 and the second input device 520 provides the voltage onthe reference line RL5 to the second load device 640.

The second sense amplifier 600 is initialized to generate the biasvoltage VB632 for setting the operating point of the first PMOStransistor 632 and the bias voltage VB642 for setting the operatingpoint of the first PMOS transistor 642 before comparing the voltageVGB5(0) on the global bit line GB5(0) with the voltage on the referenceline RLS. As shown in FIG. 2B, at the start of initializing the secondsense amplifier 600, the second sense amplifier 600 is in theinitializing configuration, the initialization signal INIT has a highlevel, the complementary initialization signal INITB has a low level,the sense amplifier enable signal SAEN transitions to a high level, thefirst power on signal PONB transitions to a high level, and the secondpower on signal NON transitions to a low level. During initializing thesecond sense amplifier 600, the bias voltage VB632 for setting theoperating point for the first PMOS transistor 632 of the first loaddevice 630 is generated and the bias voltage VB642 for setting theoperating point for the first PMOS transistor 642 of the second loaddevice 640 is generated.

The bias voltage VB632 is generated on the first line L637 and thesecond line L638 of the first load device 630 and the bias voltage VB642is generated on the first line L647 and the second line L648 of thesecond load device 640. The voltage on the first line L637 and thevoltage on the second line L638 of the first load device 630 aregenerally the same voltage because turning on the second NMOS transistor633 and the second PMOS transistor 634 electrically connects the firstPMOS transistor 632 to function as a as diode by electrically connectingthe first line L637 and the second line L638. The voltage on the firstline L647 and the voltage on the second line L648 of the second loaddevice 640 are generally the same voltage because turning on the secondNMOS transistor 643 and the second PMOS transistor 644 electricallyconnects the first PMOS transistor 642 as to function as a diode byelectrically connecting the first line L647 and the second line L648.The bias voltage VB632 is based on an amount of current flowing throughthe first load device 630 and the bias voltage VB642 is based on anamount of current flowing through the second load device 640. The sum ofthe amount of current flowing through the first load device 630 and theamount of current flowing through the second load device 640 is equal toan amount of current sunk by the current source 650.

A current path through the first load device 630 is created byelectrically connecting the first PMOS transistor 632 to function as adiode and providing the inhibit voltage VINH to the gate terminal of thefirst NMOS transistor 631. The first PMOS transistor 632 is electricallyconnected to function as a diode by turning on the second NMOStransistor 633 and the second PMOS transistor 634. The inhibit voltageVINH is provided to the gate terminal of the first NMOS transistor 631of the first load device 630 by turning off the first PMOS transistor512 of the first input device 510 and turning on the second PMOStransistor 514 of the first input device 510. The second NMOS transistor633 of the first load device 630 is turned on and the first PMOStransistor 512 of the first input device 510 is turned off because theinitialization signal INIT has a high level. The second PMOS transistor634 of the first load device 630 and the second PMOS transistor 514 ofthe first input device 510 are turned on because the complementaryinitialization signal INITB has a low level.

A current path through the second load device 640 is created byelectrically connecting the first PMOS transistor 642 to function as adiode and providing the inhibit voltage VINH to the gate terminal of thefirst NMOS transistor 641. The first PMOS transistor 642 is electricallyconnected to function as a diode by turning on the second NMOStransistor 643 and the second PMOS transistor 644. The inhibit voltageVINH is provided to the gate terminal of the first NMOS transistor 641of the second load device 640 by turning off the first PMOS transistor522 of the second input device 520 and turning on the second PMOStransistor 524 of the second input device 510. The second NMOStransistor 643 of the second load device 640 is turned on and the firstPMOS transistor 522 of the second input device 520 is turned off becausethe initialization signal INIT has a high level. The second PMOStransistor 644 of the second load device 640 and the second PMOStransistor 524 of the second input device 520 are turned on because thecomplementary initialization signal INITB has a low level.

The first voltage swing limiter 610 and the second voltage swing limiter620 limit the voltage difference between the bias voltage VB632 and thebias voltage VB642. The first voltage swing limiter 610 receives thebias voltage VB632 from the first load device 630 and outputs a voltagebased on the bias voltage VB632 to the second load device 640. Thevoltage output by the first voltage swing limiter 610 generallyincreases when the bias voltage VB632 increases and generally decreaseswhen the bias voltage VB632 decreases. The second voltage swing limiter620 receives the bias voltage VB642 from the second load device 640 andoutputs a voltage based on the bias voltage VB642 to the first loaddevice 630. The voltage output by the second voltage swing limiter 620generally increases when the bias voltage VB642 increases and generallydecreases when the bias voltage VB642 decreases.

The first capacitor connected PMOS transistor 635 and the secondcapacitor connected PMOS transistor 636 of the first load device 630 arecharged to the bias voltage VB632 because the first capacitor connectedPMOS transistor 635 and the second capacitor connected PMOS transistor636 are electrically connected to the second line L638. The bias voltageVB632 on the first line L637 and the second line L638 is approximatelyequal to the voltage on the drain terminal of the first PMOS transistor632. The first capacitor connected PMOS transistor 645 and the secondcapacitor connected PMOS transistor 646 of the second load device 640are charged to the bias voltage VB642 because the first capacitorconnected PMOS transistor 645 and the second capacitor connected PMOStransistor 646 are electrically connected to the second line L648. Thebias voltage VB642 on the first line L647 and the second line L648 isapproximately equal to the voltage on the drain terminal of the firstPMOS transistor 642.

The impact of noise and voltage offsets on the bias voltage VB632 andthe bias voltage VB642 are reduced because the first capacitor connectedPMOS transistor 635 of the first load device 630 and the first capacitorconnected PMOS transistor 645 of the second load device 640 are crosscoupled so that noise and voltage offsets on line L637 and line L638 ofthe first load device 630 are similar to noise and voltage offsets online L647 and line L648 of the second load device 640. Additionally, theimpact of noise and voltage offsets on the bias voltage VB632 and thebias voltage VB642 are reduced because the first coupling canceller 680and the second coupling canceller 690 are cross coupled so that noiseand voltage offsets on line L637 and line L638 of the first load device630 are similar to noise and voltage offsets on line L647 and line L648of the second load device 640.

The impact of voltage transients on the bias voltage VB632 and the biasvoltage VB642 are reduced by the voltage levels of the initializationsignal INIT and the complementary initialization signal INITB beingoffset. Voltage transients introduced through gate to channelcapacitance of the second NMOS transistor 633 by turning on and off thesecond NMOS transistor 633 and voltage transients introduced throughgate to channel capacitance of the second PMOS transistor 634 by turningon and off the second PMOS transistor 634 are offset because the voltagelevels of the initialization signal INIT and the complementaryinitialization signal INITB are offset. Thus, voltage transientsintroduced through gate to channel capacitance of the second NMOStransistor 633 by turning on and off the second NMOS transistor 633 andvoltage transients introduced through gate to channel capacitance of thesecond PMOS transistor 634 by turning on and off the second PMOStransistor 634 at least partially cancel each other because the voltagetransients are offset. Voltage transients introduced through gate tochannel capacitance of the second NMOS transistor 643 by turning on andoff the second NMOS transistor 643 and voltage transients introducedthrough gate to channel capacitance of the second PMOS transistor 644 byturning on and off the second PMOS transistor 644 are offset because thevoltage levels of the initialization signal INIT and the complementaryinitialization signal INITB are offset. Thus, voltage transientsintroduced through gate to channel capacitance of the second NMOStransistor 643 by turning on and off the second NMOS transistor 643 andvoltage transients introduced through gate to channel capacitance of thesecond PMOS transistor 644 by turning on and off the second PMOStransistor 644 at least partially cancel each other because the voltagetransients are offset.

After initializing the second sense amplifier 600 to generate the biasvoltage VB632 and the bias voltage VB642, the second sense amplifier 600compares the voltage VGB5(0) on the global bit line GB5(0) with thevoltage on the reference line RL5. The first PMOS transistor 632 iselectrically connected to function as a resistor with the gate voltageof the first PMOS transistor 632 kept at the bias voltage VB632 and thefirst PMOS transistor 642 is electrically connected to function as aresistor with the gate voltage of the first PMOS transistor 642 kept atthe bias voltage VB642. Keeping the gate voltage of the first PMOStransistor 632 at the bias voltage VB632 and the gate voltage of thefirst PMOS transistor 642 at the bias voltage VB642 increases theaccuracy of comparing the voltage VGB5(0) on the global bit line GB5(0)with the voltage on the reference line RL5 because keeping the gatevoltage of the first PMOS transistor 632 at the bias voltage VB632 andthe gate voltage of the first PMOS transistor 642 at the bias voltageVB642 compensates for performance differences between the first loaddevice 630 and the second load device 640.

As shown in FIG. 2B, at the start of comparing the voltage VGB5(0) onthe global bit line GB5(0) with the voltage on the reference line RL5,the initialization signal INIT transitions to a low level, thecomplementary initialization signal INITB transitions to a high level,the sense amplifier enable signal SAEN has high level, the first poweron signal PONB has a high level, and the second power on signal NON hasa low level. As discussed above, when the initialization signal INIT hasa low level and the complementary initialization signal INITB has a highlevel, the second sense amplifier 600 is in a comparing configuration,the first input device 510 provides the voltage VGB5(0) on the globalbit line GB5(0) to the first load device 630, and the second inputdevice 520 provides the voltage on the reference line RL5 to the secondload device 640. During comparing the voltage VGB5(0) on the global bitline GB5(0) with the voltage on the reference line RL5, a voltage VS637is generated on the first line L637 of the first load device 630 and avoltage VS647 is generated on the first line L647 of the second loaddevice 640 with the voltage VS637 and the voltage VS647 being indicativeof a difference between the voltage VGBS(0) on the global bit lineGB5(0) and the voltage on the reference line RLS. The voltage VS637 isbased on an amount of current flowing through the first load device 630and the voltage VS647 is based on an amount of current flowing throughthe second load device 640. The sum of the amount of current flowingthrough the first load device 630 and the amount of current flowingthrough the second load device 640 is equal to an amount of current sunkby the current source 650.

A current path through the first load device 630 is created by keepingthe gate voltage of first PMOS transistor 632 at the bias voltage VB632and providing the voltage VGBS(0) on the global bit line GB5(0) to thegate terminal of the first NMOS transistor 631. The gate voltage of thefirst PMOS transistor 632 is kept at the bias voltage VB632 bydisconnecting the first line L637 from the second line L638 with thefirst capacitor connected PMOS transistor 635 and the second capacitorconnected PMOS transistor 636 charged to the bias voltage VB632. Afterdisconnecting the first line L637 from the second line L638 the voltageon the second line L638 and the gate voltage of the first PMOStransistor 632 are kept at the bias voltage VB632 by the first capacitorconnected PMOS transistor 635 and the second capacitor connected PMOStransistor 636. The first line L637 is disconnected from the second lineL638 by turning off the second NMOS transistor 633 and the second PMOStransistor 634. The voltage VGBS(0) on the global bit line GB5(0) isprovided to the gate terminal of the first NMOS transistor 631 byturning on the first PMOS transistor 512 of the first input device 510and turning off the second PMOS transistor 514 of the first input device510. The voltage VGBS(0) on the global bit line GB5(0) is driven to avoltage indicative of a resistive state of the resistive change elementO01 as discussed above with respect to generating a voltage indicativeof a resistive state of the resistive change element O01. The secondNMOS transistor 633 of the first load device 630 is turned off and thefirst PMOS transistor 512 of the first input device 510 is turned onbecause the initialization signal INIT has a low level. The second PMOStransistor 634 of the first load device 630 and the second PMOStransistor 514 of the first input device 510 are turned off because thecomplementary initialization signal INITB has a high level.

A current path through the second load device 640 is created by keepingthe gate voltage of first PMOS transistor 642 at the bias voltage VB642and providing the voltage on the reference line RL5 to the gate terminalof the first NMOS transistor 641. The gate voltage of the first PMOStransistor 642 is kept at the bias voltage VB642 by disconnecting thefirst line L647 from the second line L648 with the first capacitorconnected PMOS transistor 645 and the second capacitor connected PMOStransistor 646 charged to the bias voltage VB642. After disconnectingthe first line L647 from the second line L648 the voltage on the secondline L648 and the gate voltage of the first PMOS transistor 642 are keptat the bias voltage VB642 by the first capacitor connected PMOStransistor 645 and the second capacitor connected PMOS transistor 646.The first line L647 is disconnected from the second line L648 by turningoff the second NMOS transistor 643 and the second PMOS transistor 644.The voltage on the reference line RL5 is provided to the gate terminalof the first NMOS transistor 641 of the second load device 640 byturning on the first PMOS transistor 522 of the second input device 520and turning off the second PMOS transistor 524 of the second inputdevice 520. The voltage on the reference line RL5 is driven to theinhibit voltage VINH by turning on the second NMOS transistor 122 in thereference line connection circuit 120 and the second NMOS transistor 122may be turned on as part of preparing the exemplary implementation ofthe second exemplary architecture for determining a resistive state ofthe resistive change element O01 as discussed above. The second NMOStransistor 643 of the second load device 640 is turned off and the firstPMOS transistor 522 of the second input device 510 is turned on becausethe initialization signal INIT has a low level. The second PMOStransistor 644 of the second load device 640 and the second PMOStransistor 524 of the second input device 520 are turned off because thecomplementary initialization signal INITB has a high level.

The amount of current flowing through the first load device 630 and theamount of current flowing through the second load device 640 generallychange when the voltage VGB5(0) on the global bit line GB5(0) changesbecause the voltage on the reference line RL5 is the inhibit voltageVINH and the inhibit voltage VINH is generally the same for READoperations. When the voltage VGB5(0) on the global bit line GB5(0)increases, the amount of current flowing through the first load device630 increases, the amount of current flowing through the second loaddevice 640 decreases, the voltage VS637 on the first line L637 of thefirst load device 630 decreases, and the voltage VS647 on the first lineL647 of the second load device 640 increases. When the voltage VGB5(0)on the global bit line GB5(0) decreases, the amount of current flowingthrough first load device 630 decreases, the amount of current flowingthrough the second load device 640 increases, the voltage VS637 on thefirst line L637 of the first load device 630 increases, and the voltageVS647 on the first line L647 of the second load device 640 decreases.

The difference between the voltage VS637 on the first line L637 in thefirst load device 630 and the voltage VS647 on the first line L647 inthe second load device 640 is indicative of a resistive state of theresistive change element O01. When the resistive change element O01 hasa low resistive state, the voltage VGB5(0) on the global bit line GB5(0)is greater than the inhibit voltage VINH, the amount of current flowingthrough the first load device 630 is greater than the amount of currentflowing through the second load device 640 and the voltage VS637 onfirst line L637 of the first load device 630 is less than the voltageVS647 on the first line L647 of the second load device 640. When theresistive change element O01 has a high resistive state, the voltageVGB5(0) on the global bit line GB5(0) is less than the inhibit voltageVINH, the amount of current flowing through the first load device 630 isless than the amount of current flowing through the second load device640 and the voltage VS637 on first line L637 of the first load device630 is greater than the voltage VS647 on the first line L647 of thesecond load device 640.

The first voltage swing limiter 610 and the second voltage swing limiter620 limit the voltage difference between the voltage VS637 generated onthe first line L637 of the first load device 630 and the voltage VS647generated on the first line L647 of the second load device 640. Thefirst voltage swing limiter 610 receives the voltage VS637 from thefirst load device 630 and outputs a voltage based on the voltage VS637to the second load device 640. The voltage output by the first voltageswing limiter 610 generally increases when the voltage VS637 increasesand generally decreases when the voltage VS637 decreases. The secondvoltage swing limiter 620 receives the voltage VS647 from the secondload device 640 and outputs a voltage based on the voltage VS647 to thefirst load device 630. The voltage output by the second voltage swinglimiter 620 generally increases when the voltage VS647 increases andgenerally decreases when the voltage VS647 decreases. Additionally, theimpact of noise and voltage offsets on the voltage VS637 and the voltageVS647 are reduced because the first coupling canceller 680 and thesecond coupling canceller 690 are cross coupled so that noise andvoltage offsets on line L637 of the first load device 630 are similar tonoise and voltage offsets on line L647 of the second load device 640.

While the first power on signal PONB has a high level, the power controldevice 660 provides the voltage VS637 to the first output 601, the gateterminal of the second PMOS transistor 676 of the latch device 670, andthe gate terminal of the second NMOS transistor 678 of the latch device670 because the second NMOS transistor 667 of the power control device660 is turned on. Also, while the first power on signal PONB has a highlevel, the power control device 660 provides the voltage VS647 to thesecond output 602, the gate terminal of the first PMOS transistor 672 ofthe latch device 670, and the gate terminal of the first NMOS transistor674 of the latch device 670 because the third NMOS transistor 668 of thepower control device 660 is turned on. When resistive change element O01has a low resistive state, the voltage VS637 has a voltage level lessthan a voltage level of the voltage VS647, the gate voltage of the firstPMOS transistor 672 is greater than the gate voltage of the second PMOStransistor 676 and the first PMOS transistor 672 is turned on less thanthe second PMOS transistor 676. Additionally, when resistive changeelement O01 has a low resistive state, the gate voltage of the firstNMOS transistor 674 is greater than the gate voltage of the second NMOStransistor 678 and the first NMOS transistor 674 is turned on greaterthan the second NMOS transistor 678. When resistive change element O01has a high resistive state, the voltage VS637 has a voltage levelgreater than a voltage level of the voltage VS647, the gate voltage ofthe first PMOS transistor 672 is less than the gate voltage of thesecond PMOS transistor 676 and the first PMOS transistor 672 is turnedon greater than the second PMOS transistor 676. Additionally, when theresistive change element O01 has a high resistive state, the gatevoltage of the first NMOS transistor 674 is less than the gate voltageof the second NMOS transistor 678 and the first NMOS transistor 674 isturned on less than the second NMOS transistor 678. During comparing thevoltage VGB5(0) on the global bit line GB5(0) with the voltage on thereference line RL5, current generally does not flow through the latchdevice 670 because the first PMOS transistor 662 of the power controldevice 660 and the first NMOS transistor 664 of the power control device660 are turned off. The first PMOS transistor 662 of the power controldevice 660 is turned off because the first power on signal PONB has ahigh level and the first NMOS transistor 664 of the power control device660 is turned off because the second power on signal NON has a lowlevel.

As shown in FIG. 2B, at the conclusion of comparing the voltage VGB5(0)on the global bit line GB5(0) with the voltage on the reference lineRL5, the initialization signal INIT transitions to a low level, thecomplementary initialization signal INITB transitions to a high level,the sense amplifier enable signal SAEN transitions to a low level, thefirst power on signal PONB transitions to a low level, and after a smalldelay the second power on signal NON transitions to a high level. Asdiscussed above, when the initialization signal INIT has a high leveland the complementary initialization signal INITB has a low level, thesecond sense amplifier 600 is in an initializing configuration, thefirst input device 510 provides the inhibit voltage VINH to the firstload device 630, and the second input device 520 provides the inhibitvoltage VINH to the second input device 640. Additionally, when thefirst power on signal PONB has a low level, the latch device 670 isdisconnected from the first load device 630 and the second load device640 and the latch device 670 is in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The latch device 670 is disconnectedfrom the first load device 630 by turning off the second NMOS transistor667 of the power control device 660 and the latch device 670 isdisconnected from the second load device 640 by turning off the thirdNMOS transistor 668. The latch device 670 is electrically connected to apower supply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD by turning on the PMOS transistor 662 ofthe power control device 660. The PMOS transistor 662 is turned on, thesecond NMOS transistor 667 is turned off, and the third NMOS transistor668 is turned off because the first power on signal PONB has a lowlevel. Further, when the second power on signal NON has a high level,the latch device 670 is in electrical communication with a power supply,a voltage source, a driver circuit, or other device that supplies 0volts or ground. The latch device 670 is electrically connected to thepower supply, the voltage source, the driver circuit, or other devicethat supplies the 0 volts or ground by turning on the first NMOStransistor 664 of the power control device 660. The first NMOStransistor 664 is turned on because the second power on signal NON has ahigh level.

When comparing the voltage VGB5(0) on the global bit line GB5(0) withthe voltage on the reference line RL5 concludes, the voltage on thefirst output 601, the voltage on the gate terminal of the second PMOStransistor 676, and the voltage on the gate terminal of the second NMOStransistor 678 are approximately equal to the voltage VS637 and thevoltage on the second output 602, the voltage on the gate terminal ofthe first PMOS transistor 672, and the voltage on the gate terminal ofthe first NMOS transistor 674 are approximately equal to the voltageVS647. The voltage difference between the voltage VS637 and the voltageVS647 can be increased by having a small delay between the first poweron signal PONB transitioning to a low level and the second power onsignal NON transitioning to high level. During the small delay, currentcan flow from the power supply, the voltage source, the driver circuit,or other device that supplies the system voltage VDD through the PMOStransistor 662 of the power control device 660 and the first PMOStransistor 672 of the latch device 670 and pull up the voltages on thefirst output 601, the gate terminal of the second PMOS transistor 676,and the gate terminal of the second NMOS transistor 678. Also, duringthe small delay, current can flow from the power supply, the voltagesource, the driver circuit, or other device that supplies the systemvoltage VDD through the PMOS transistor 662 of the power control device660 and the second PMOS transistor 676 of the latch device 670 and pullup the voltages on the second output 602, the gate terminal of the firstPMOS transistor 672, and the gate terminal of the first NMOS transistor674. When the voltage level of the voltage VS637 is less than thevoltage level of the voltage VS647, the first PMOS transistor 672 isturned on less than the second PMOS transistor 676 and the voltages onthe first output 601, the gate terminal of the second PMOS transistor676, and the gate terminal of the second NMOS transistor 678 are pulledup less than the voltages on the second output 602, the gate terminal ofthe first PMOS transistor 672, and the gate terminal of the first NMOStransistor 674 because an amount of current flowing through the firstPMOS transistor 672 is less than an amount of current flowing throughthe second PMOS transistor 676. When the voltage level of the voltageVS637 is greater than the voltage level of the voltage VS647, the firstPMOS transistor 672 is turned on greater than the second PMOS transistor676 and the voltages on the first output 601, the gate terminal of thesecond PMOS transistor 676, and the gate terminal of the second NMOStransistor 678 are pulled up greater than the voltages on the secondoutput 602, the gate terminal of the first PMOS transistor 672, and thegate terminal of the first NMOS transistor 674 because an amount ofcurrent flowing through the first PMOS transistor 672 is greater than anamount of current flowing through the second PMOS transistor 676.Alternatively, the first power on signal PONB transitioning to a lowlevel and the second power on signal NON transitioning to a high levelcan occur at approximately the same time.

After the first power on signal PONB has a low level and the secondpower on signal NON has a high level, the voltages on the first output601, the gate terminal of the second PMOS transistor 676, and the gateterminal of the second NMOS transistor 678 transition to the systemvoltage VDD or 0 volts or ground and the voltages on the second output602, the gate terminal of the first PMOS transistor 672, and the gateterminal of the first NMOS transistor 674 transition to the systemvoltage VDD or 0 volts or ground. When the resistive change element O01has a low resistive state the voltage on the first output 601, the gateterminal of the second PMOS transistor 676, and the gate terminal of thesecond NMOS transistor 678 transition to 0 volts or ground and thevoltages on the second output 602, the gate terminal of the first PMOStransistor 672, and the gate terminal of the first NMOS transistor 674transition to the system voltage VDD because the first PMOS transistor672 is turned on less than the second PMOS transistor 676 and the firstNMOS transistor 674 is turned on greater than the second NMOS transistor678. The voltage on the first output 601 being 0 volts or ground and thevoltage on the second output 602 being the system voltage VDD is storedin the latch device 670 by the first PMOS transistor 672 being turnedoff, the first NMOS transistor 674 being turned on, the second PMOStransistor 676 being turned on, and the second NMOS transistor 678 beingturned off. Additionally, the voltage on the first output 601 isgenerally kept at 0 volts or ground and the voltage on the second output602 is generally kept at the system voltage VDD by the first PMOStransistor 672 being turned off, the first NMOS transistor 674 beingturned on, the second PMOS transistor 676 being turned on, and thesecond NMOS transistor 678 being turned off. Therefore, when resistivechange element O01 has a low resistive state the second sense amplifier600 outputs 0 volts or ground on the first output 601 and the systemvoltage VDD on the second output 602.

When the resistive change element O01 has a high resistive state thevoltage on the first output 601, the gate terminal of the second PMOStransistor 676, and the gate terminal of the second NMOS transistor 678transition to the system voltage VDD and the voltages on the secondoutput 602, the gate terminal of the first PMOS transistor 672, and thegate terminal of the first NMOS transistor 674 transition to 0 volts orground because the first PMOS transistor 672 is turned on greater thanthe second PMOS transistor 676 and the first NMOS transistor 674 isturned on less than the second NMOS transistor 678. The voltage on thefirst output 601 being the system voltage VDD and the voltage on thesecond output 602 being 0 volts or ground is stored in the latch device670 by the first PMOS transistor 672 being turned on, the first NMOStransistor 674 being turned off, the second PMOS transistor 676 beingturned off, and the second NMOS transistor 678 being turned on.Additionally, the voltage on the first output 601 is generally kept thesystem voltage VDD and the voltage on the second output 602 is generallykept 0 volts or ground by the first PMOS transistor 672 being turned on,the first NMOS transistor 674 being turned off, the second PMOStransistor 676 being turned off, and the second NMOS transistor 678being turned on. Therefore, when resistive change element O01 has a highresistive state the second sense amplifier 600 outputs the systemvoltage VDD on the first output 601 and 0 volts or ground on the secondoutput 602.

Referring now to FIG. 7, the third sense amplifier 700 receives avoltage V510 provided by the first input device 510, a voltage V520provided by the second input device 520, an initialization signal INIT,a complementary initialization signal INITB, a first power on signalPONB, a second power on signal NON, a sense amplifier enable signalSAEN, and a bias current signal BIAS, and outputs a voltage VoutB and avoltage Vout. The third sense amplifier 700 includes a first voltageswing limiter 710, a second voltage swing limiter 720, a first loaddevice 730, a second load device 740, a current source 750, a firstcoupling canceller 780, a second coupling canceller 790, a power controldevice 760, and a latch device 770. The first voltage swing limiter 710includes a NMOS transistor 711 having a drain terminal, a gate terminal,and a source terminal and a PMOS transistor 712 having a drain terminal,a gate terminal, and a source terminal. The drain terminal of the NMOStransistor 711 is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies thesystem voltage VDD. The gate terminal of the NMOS transistor 711 is inelectrical communication with the first load device 730 and the gateterminal of the PMOS transistor 712. The source terminal of the NMOStransistor 711 is in electrical communication with the second loaddevice 740 and the source terminal of the PMOS transistor 712. The drainterminal of the PMOS transistor 712 is in electrical communication witha power supply, a voltage source, a driver circuit, or other device thatsupplies 0 volts or ground. The gate terminal of the PMOS transistor 712is in electrical communication with the first load device 730 and thegate terminal of the NMOS transistor 711. The source terminal of thePMOS transistor 712 is in electrical communication with the second loaddevice 740 and the source terminal of the NMOS transistor 711.

The second voltage swing limiter 720 includes a NMOS transistor 721having a drain terminal, a gate terminal, and a source terminal and aPMOS transistor 722 having a drain terminal, a gate terminal, and asource terminal. The drain terminal of the NMOS transistor 721 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies the system voltage VDD. The gateterminal of the NMOS transistor 721 is in electrical communication withthe second load device 740 and the gate terminal of the PMOS transistor722. The source terminal of the NMOS transistor 721 is in electricalcommunication with the first load device 730 and the source terminal ofthe PMOS transistor 622. The drain terminal of the PMOS transistor 722is in electrical communication with a power supply, a voltage source, adriver circuit, or other device that supplies 0 volts or ground. Thegate terminal of the PMOS transistor 722 is in electrical communicationwith the second load device 740 and the gate terminal of the NMOStransistor 721. The source terminal of the PMOS transistor 722 is inelectrical communication with the first load device 730 and the sourceterminal of the NMOS transistor 721.

The first load device 730 includes a first NMOS transistor 731 having adrain terminal, a gate terminal, and a source terminal, a first PMOStransistor 732 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 733 having a drain terminal, a gateterminal, and a source terminal, a second PMOS transistor 734 having adrain terminal, a gate terminal, and a source terminal, a firstcapacitor connected PMOS transistor 735 having a drain terminal, a gateterminal, and a source terminal, and a second capacitor connected PMOStransistor 736 having a drain terminal, a gate terminal, and a sourceterminal, a third NMOS transistor 737 having a drain terminal, a gateterminal, and a source terminal, and a capacitor connected NMOStransistor 738 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 731 is inelectrical communication with the drain terminal of the third NMOStransistor 737, the first coupling canceller 780, the second voltageswing limiter 720, the power control device 760, the first voltage swinglimiter 710, the second load device 740, the drain terminal of the firstPMOS transistor 732, the drain terminal of the second PMOS transistor734, and the source terminal of the second NMOS transistor 733. The gateterminal of the first NMOS transistor 731 is in electrical communicationwith the source terminal of the third NMOS transistor 737, the secondcoupling canceller 790, and the drain terminal and the source terminalof the capacitor connected NMOS transistor 738. The source terminal ofthe first NMOS transistor 731 is in electrical communication with thecurrent source 750 and the second load device 740. The drain terminal ofthe first PMOS transistor 732 is in electrical communication with thedrain terminal of the second PMOS transistor 734, the source terminal ofthe second NMOS transistor 733, the second load device 740, the firstvoltage swing limiter 710, the power control device 760, the secondvoltage swing limiter 720, the first coupling canceller 780, and thedrain terminal of the first NMOS transistor 731. The gate terminal ofthe first PMOS transistor 732 is in electrical communication with thesource terminal of the second PMOS transistor 734, the drain terminal ofthe second NMOS transistor 733, the gate terminal of first capacitorconnected PMOS transistor 735, and the gate terminal of the secondcapacitor connected PMOS transistor 736. The source terminal of thefirst PMOS transistor 732 is in electrical communication with a powersupply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The drain terminal of the second NMOStransistor 733 is in electrical communication with the source terminalof the second PMOS transistor 734, the gate terminal of the first PMOStransistor 632, the gate terminal of the first capacitor connected PMOStransistor 735, and the gate terminal of the second capacitor connectedPMOS transistor 736. The gate terminal of the second NMOS transistor 733is in electrical communication with control logic, such as a processor,a controller, and a microcontroller, to receive the initializationsignal INIT. The source terminal of the second NMOS transistor 733 is inelectrical communication with the drain terminal of the second PMOStransistor 734, the drain terminal of the first PMOS transistor 732, thesecond load device 740, the first voltage swing limiter 710, the powercontrol device 760, the second voltage swing limiter 720, the firstcoupling canceller 780, the drain terminal of the third NMOS transistor737, and the drain terminal of the first NMOS transistor 731. The drainterminal of the second PMOS transistor 734 is in electricalcommunication with the source terminal of the second NMOS transistor733, the drain terminal of the first PMOS transistor 732, the secondload device 740, the first voltage swing limiter 710, the power controldevice 760, the second voltage swing limiter 720, the first couplingcanceller 780, the drain terminal of the third NMOS transistor 737, andthe drain terminal of the first NMOS transistor 731. The gate terminalof the second PMOS transistor 734 is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive the complementary initialization signal INITB. The sourceterminal of the second PMOS transistor 734 is in electricalcommunication with the gate terminal of the first PMOS transistor 732,the drain terminal of the second NMOS transistor 733, the gate terminalof the first capacitor connected PMOS transistor 735, and the gateterminal of the second capacitor connected PMOS transistor 736. Thedrain terminal and the source terminal of the first capacitor connectedPMOS transistor 735 are in electrical communication and the drainterminal and the source terminal are in electrical communication withthe second load device 740. The gate terminal of the first capacitorconnected PMOS transistor 735 is in electrical communication with thedrain terminal of the second NMOS transistor 733, the source terminal ofthe second PMOS transistor 734, the gate terminal of the first PMOStransistor 732, and the gate terminal of the second capacitor connectedPMOS transistor 736. The drain terminal and the source terminal of thesecond capacitor connected PMOS transistor 736 are in electricalcommunication and the drain terminal and the source terminal are inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies the system voltage VDD. The gateterminal of the second capacitor connected PMOS transistor 736 is inelectrical communication with the gate terminal of the first PMOStransistor 732, the source terminal of the second PMOS transistor 734,the drain terminal of the second NMOS transistor 733, and the gateterminal of the first capacitor connected PMOS transistor 735. The drainterminal of the third NMOS transistor 737 is in electrical communicationwith the drain terminal of the first NMOS transistor 731, the firstcoupling canceller 780, the second voltage swing limiter 720, the powercontrol device 760, the first voltage swing limiter 710, the second loaddevice 740, the drain terminal of the first PMOS transistor 732, thedrain terminal of the second PMOS transistor 734, and the sourceterminal of the second NMOS transistor 733. The gate terminal of thethird NMOS transistor 737 is in electrical communication with controllogic, such as a processor, a controller, and a microcontroller, toreceive the initialization signal INIT. The source terminal of the thirdNMOS transistor 737 is in electrical communication with the gateterminal of the first NMOS transistor 731, the second coupling canceller790, and the drain terminal and the source terminal of the capacitorconnected NMOS transistor 738. The drain terminal and the sourceterminal of the capacitor connected NMOS transistor 738 are inelectrical communication and the drain terminal and the source terminalare in electrical communication with the second coupling canceller 790,the source terminal of the third NMOS transistor 738, and the gateterminal of the first NMOS transistor 731. The gate terminal of thecapacitor connected NMOS transistor 738 is in electrical communicationwith the first input device 510.

The second load device 740 includes a first NMOS transistor 741 having adrain terminal, a gate terminal, and a source terminal, a first PMOStransistor 742 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 743 having a drain terminal, a gateterminal, and a source terminal, a second PMOS transistor 744 having adrain terminal, a gate terminal, and a source terminal, a firstcapacitor connected PMOS transistor 745 having a drain terminal, a gateterminal, and a source terminal, and a second capacitor connected PMOStransistor 746 having a drain terminal, a gate terminal, and a sourceterminal, a third NMOS transistor 747 having a drain terminal, a gateterminal, and a source terminal, and a capacitor connected NMOStransistor 748 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 741 is inelectrical communication with the drain terminal of the third NMOStransistor 747, the second coupling canceller 790, the first voltageswing limiter 710, the power control device 760, the second voltageswing limiter 720, the first load device 730, the drain terminal of thefirst PMOS transistor 742, the drain terminal of the second PMOStransistor 744, and the source terminal of the second NMOS transistor743. The gate terminal of the first NMOS transistor 741 is in electricalcommunication with the source terminal of the third NMOS transistor 737,the first coupling canceller 780, and the drain terminal and the sourceterminal of the capacitor connected NMOS transistor 748. The sourceterminal of the first NMOS transistor 741 is in electrical communicationwith the current source 750 and the first load device 730. The drainterminal of the first PMOS transistor 742 is in electrical communicationwith the drain terminal of the second PMOS transistor 744, the sourceterminal of the second NMOS transistor 743, the first load device 730,the second voltage swing limiter 720, the power control device 760, thefirst voltage swing limiter 710, the second coupling canceller 790, thedrain terminal of the third NMOS transistor 747, and the drain terminalof the first NMOS transistor 741. The gate terminal of the first PMOStransistor 742 is in electrical communication with the source terminalof the second PMOS transistor 744, the drain terminal of the second NMOStransistor 743, the gate terminal of the first capacitor connected PMOStransistor 745, and the gate terminal of the second capacitor connectedPMOS transistor 746. The source terminal of the first PMOS transistor742 is in electrical communication with a power supply, a voltagesource, a driver circuit, or other device that supplies the systemvoltage VDD. The drain terminal of the second NMOS transistor 743 is inelectrical communication with the source terminal of the second PMOStransistor 744, the gate terminal of the first PMOS transistor 742, thegate terminal of the first capacitor connected PMOS transistor 745, andthe gate terminal of the second capacitor connected PMOS transistor 746.The gate terminal of the second NMOS transistor 743 is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive the initialization signal INIT. The sourceterminal of the second NMOS transistor 743 is in electricalcommunication with the drain terminal of the second PMOS transistor 744,the drain terminal of the first PMOS transistor 742, the first loaddevice 730, the second voltage swing limiter 720, the power controldevice 760, the first voltage swing limiter 710, the second couplingcanceller 790, the drain terminal of the third NMOS transistor 737, andthe drain terminal of the first NMOS transistor 741. The drain terminalof the second PMOS transistor 744 is in electrical communication withthe source terminal of the second NMOS transistor 743, the drainterminal of the first PMOS transistor 742, the first load device 730,the second voltage swing limiter 720, the power control device 760, thefirst voltage swing limiter 710, the second coupling canceller 790, thedrain terminal of the third NMOS transistor 747, and the drain terminalof the first NMOS transistor 741. The gate terminal of the second PMOStransistor 744 is in electrical communication with control logic, suchas a processor, a controller, and a microcontroller, to receive thecomplementary initialization signal INITB. The source terminal of thesecond PMOS transistor 744 is in electrical communication with the gateterminal of the first PMOS transistor 742, the drain terminal of thesecond NMOS transistor 743, the gate terminal of the first capacitorconnected PMOS transistor 745, and the gate terminal of the secondcapacitor connected PMOS transistor 746. The drain terminal and thesource terminal of the first capacitor connected PMOS transistor 745 arein electrical communication and the drain terminal and the sourceterminal are in electrical communication with the first load device 730.The gate terminal of the first capacitor connected PMOS transistor 745is in electrical communication with the drain terminal of the secondNMOS transistor 743, the source terminal of the second PMOS transistor744, the gate terminal of the first PMOS transistor 742, and the gateterminal of the second capacitor connected PMOS transistor 746. Thedrain terminal and the source terminal of the second capacitor connectedPMOS transistor 746 are in electrical communication and the drainterminal and the source terminal are in electrical communication with apower supply, a voltage source, a driver circuit, or other device thatsupplies the system voltage VDD. The gate terminal of the secondcapacitor connected PMOS transistor 746 is in electrical communicationwith the gate terminal of the first PMOS transistor 742, the sourceterminal of the second PMOS transistor 744, the drain terminal of thesecond NMOS transistor 743, and the gate terminal of the first capacitorconnected PMOS transistor 745. The drain terminal of the third NMOStransistor 747 is in electrical communication with the drain terminal ofthe first NMOS transistor 741, the second coupling canceller 790, thefirst voltage swing limiter 710, the power control device 760, thesecond voltage swing limiter 720, the drain terminal of the first PMOStransistor 742, the drain terminal of the second PMOS transistor 744,and the source terminal of the second NMOS transistor 743. The gateterminal of the third NMOS transistor 747 is in electrical communicationwith control logic, such as a processor, a controller, and amicrocontroller, to receive the initialization signal INIT. The sourceterminal of the third NMOS transistor 747 is in electrical communicationwith the gate terminal of the first NMOS transistor 741, the firstcoupling canceller 780, and the drain terminal and the source terminalof the capacitor connected NMOS transistor 748. The drain terminal andthe source terminal of the capacitor connected NMOS transistor 748 arein electrical communication and the drain terminal and the sourceterminal are in electrical communication with the first couplingcanceller 780, the source terminal of the third NMOS transistor 747, andthe gate terminal of the first NMOS transistor 741. The gate terminal ofthe capacitor connected NMOS transistor 748 is in electricalcommunication with the second input device 520.

The current source 750 includes a first NMOS transistor 752 have a drainterminal, a gate terminal, and a source terminal and a second NMOStransistor 754 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal of the first NMOS transistor 752 is inelectrical communication with the first load device 730 and the secondload device 740. The gate terminal of the first NMOS transistor 752 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the sense amplifier enablesignal SAEN. The source terminal of the first NMOS transistor 752 is inelectrical communication with the drain terminal of the second NMOStransistor 754. The drain terminal of the second NMOS transistor 754 isin electrical communication with the source terminal of the first NMOStransistor 752. The gate terminal of the second NMOS transistor 754 isin electrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the bias current signalBIAS. The source terminal of the second NMOS transistor 754 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground.

The first coupling canceller 780 includes a capacitor connected NMOStransistor 781 having a drain terminal, a gate terminal, and a sourceterminal. The drain terminal and the source terminal of the capacitorconnected NMOS transistor 781 are in electrical communication and thedrain terminal and the source terminal are in electrical communicationwith the second input device 520 and the second load device 740. Thegate terminal of the first capacitor connected NMOS transistor 781 is inelectrical communication with the first load device 730. The secondcoupling canceller 790 includes a capacitor connected NMOS transistor791 having a drain terminal, a gate terminal, and a source terminal. Thedrain terminal and the source terminal of the capacitor connected NMOStransistor 791 are in electrical communication and the drain terminaland the source terminal are in electrical communication with the firstinput device 510 and the first load device 730. The gate terminal of thecapacitor connected NMOS transistor 791 is in electrical communicationwith the second load device 740.

The power control device 760 includes a PMOS transistor 762 having adrain terminal, a gate terminal, and a source terminal, a first NMOStransistor 764 having a drain terminal, a gate terminal, and a sourceterminal, a second NMOS transistor 767 having a drain terminal, a gateterminal, and a source terminal, and a third NMOS transistor 768 havinga drain terminal, a gate terminal, and a source terminal. The drainterminal of the PMOS transistor 762 is in electrical communication withthe latch device 770. The gate terminal of the PMOS transistor 762 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive the first power on signalPONB. The source terminal of the PMOS transistor 762 is in electricalcommunication with a power supply, a voltage source, a driver circuit,or other device that supplies the system voltage VDD. The drain terminalof the first NMOS transistor 764 is in electrical communication with thelatch device 770. The gate terminal of the first NMOS transistor 764 isin electrical communication control logic, such as a processor, acontroller, and a microcontroller, to receive the second power on signalNON. The source terminal of the first NMOS transistor 764 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies 0 volts or ground. The drainterminal of the second NMOS transistor 767 is in electricalcommunication with the latch device 770. The gate terminal of the secondNMOS transistor 767 is in electrical communication with control logic,such as a processor, a controller, and a microcontroller, to receive thefirst power on signal PONB. The source terminal of the second NMOStransistor 767 is in electrical communication with the first load device730. The drain terminal of the third NMOS transistor 768 is inelectrical communication with the second load device 740. The gateterminal of the third NMOS transistor 768 is in electrical communicationwith control logic, such as a processor, a controller, and amicrocontroller, to receive the first power on signal PONB. The sourceterminal of the third NMOS transistor 768 is in electrical communicationwith the latch device 770. Alternatively, each of the second NMOStransistor 767 and the third NMOS transistor 768 may be replaced with aNMOS transistor and a PMOS transistor in electrical communication inparallel, with each of the NMOS transistors having a drain terminal, agate terminal, and a source terminal, each of the PMOS transistorshaving a drain terminal, a gate terminal, and a source terminal, thegate terminals of both NMOS transistors in electrical communication witha circuit to receive a signal to turn on and turn off both NMOStransistors, the gate terminals of both PMOS transistors in electricalcommunication with a circuit to receive a signal to turn on and turn offboth PMOS transistors, and the signals being coordinated such that bothNMOS transistors and both PMOS transistors are turned on and turned offat generally the same time.

The latch device 770 includes a first PMOS transistor 772 having a drainterminal, a gate terminal, and a source terminal, a first NMOStransistor 774 having a drain terminal, a gate terminal, and a sourceterminal, a second PMOS transistor 776 having a drain terminal, a gateterminal, and a source terminal, and a second NMOS transistor 778 havinga drain terminal, a gate terminal, and a source terminal. The drainterminal of the first PMOS transistor 772 is in electrical communicationwith the gate terminal of the second PMOS transistor 776, the gateterminal of the second NMOS transistor 778, the power control device760, and the drain terminal of the first NMOS transistor 774. The gateterminal of the first PMOS transistor 772 is in electrical communicationwith the drain terminal of the second PMOS transistor 776, the drainterminal of the second NMOS transistor 778, the power control device760, and the gate terminal of the first NMOS transistor 774. The sourceterminal of the first PMOS transistor 772 is in electrical communicationwith the power control device 760 and the source terminal of the secondPMOS transistor 776. The drain terminal of the first NMOS transistor 774is in electrical communication with the power control device 760, thegate terminal of the second PMOS transistor 776, the gate terminal ofthe second NMOS transistor 778, and the drain terminal of the first PMOStransistor 772. The gate terminal of the first NMOS transistor 774 is inelectrical communication with the drain terminal of the second PMOStransistor 776, the drain terminal of the second NMOS transistor 778,the power control device 760, and the gate terminal of the first PMOStransistor 772. The source terminal of the first NMOS transistor 774 isin electrical communication with the power control device 760 and thesource terminal of the second NMOS transistor 778. The drain terminal ofthe second PMOS transistor 776 is in electrical communication with thepower control device 760, the gate terminal of the first PMOS transistor772, the gate terminal of the first NMOS transistor 774, and the drainterminal of the second NMOS transistor 778. The gate terminal of thesecond PMOS transistor 776 is in electrical communication with the drainterminal of the first PMOS transistor 772, the drain terminal of thefirst NMOS transistor 774, the power control device 760, and the gateterminal of the second NMOS transistor 778. The source terminal of thesecond PMOS transistor 776 is in electrical communication with the powercontrol device 760 and the source terminal of the first PMOS transistor772. The drain terminal of the second NMOS transistor 778 is inelectrical communication with the power control device 760, the gateterminal of the first PMOS transistor 772, the gate terminal of thefirst NMOS transistor 774, and the drain terminal of the second PMOStransistor 776. The gate terminal of the second NMOS transistor 778 isin electrical communication with the drain terminal of the first PMOStransistor 772, the drain terminal of the first NMOS transistor 774, thepower control device 760, and the gate terminal of the second PMOStransistor 776. The source terminal of the second NMOS transistor 778 isin electrical communication with the power control device 760 and thesource terminal of the first NMOS transistor 774.

Referring to the simplified schematic diagram of the third senseamplifier 700 shown in FIG. 7, the first load device 730 receives thevoltage V510 provided by the first input device 510, the initializationsignal INIT, and the complementary initialization signal INITB. Thesecond load device 740 receives the voltage V520 provided by the secondinput device 520, the initialization signal INIT, and the complementaryinitialization signal INITB. The current source 750 receives the senseamplifier enable signal SAEN and the bias current signal BIAS. The powercontrol device 760 receives the first power on signal PONB and thesecond power on signal NON. Control logic, such as a processor, acontroller, and a microcontroller, supplies the initialization signalINIT, the complementary initialization signal INITB, the sense amplifierenable signal SAEN, the bias current signal BIAS, the first power onsignal PONB, and the second power on signal NON to the third senseamplifier 700. Exemplary voltage waveforms for the initialization signalINIT, the complementary initialization signal INITB, the sense amplifierenable signal SAEN, the first power on signal PONB, and the second poweron signal NON for describing operation of the third sense amplifier 700for READ operations of resistive change element O01 are shown in FIG.2B. Additionally, although an exemplary voltage waveform for the biascurrent signal BIAS is not shown in FIG. 2B, the control logic suppliesthe bias current signal BIAS. The control logic supplies the senseamplifier enable signal SAEN to enable and disable the current source750 and the bias current signal BIAS to set the amount of current sunkby the current source 750. Also, exemplary voltage waveforms for thesignal YD0, the signal SSELo, the signal KEEPe, the voltage VW(1) on theword line W(1), the voltage on the reference line RL5 labeled as thevoltage REF, and the voltage VGBS(0) on the global bit line GB5(0)labeled as the voltage VGB for describing operation of the third senseamplifier 700 for READ operations of resistive change element O01 areshown in FIG. 2B. Further, FIG. 2B shows two exemplary voltage waveformsfor the voltage VGB, a voltage waveform for when the resistive changeelement O01 has a low resistive state and a voltage waveform for whenthe resistive change element O01 has a high resistive state.

The third sense amplifier 700 is in an initializing configuration whenthe initialization signal INIT has a high level and the complementaryinitialization signal INITB has a low level and the third senseamplifier 700 is in a comparing configuration when the initializationsignal INIT has a low level and the complementary initialization signalINITB has a high level. When the third sense amplifier 700 is in aninitializing configuration the first PMOS transistor 732 and the thirdNMOS transistor 737 of the first load device 730 are electricallyconnected to function as diodes and the first PMOS transistor 742 andthe third NMOS transistor 747 of the second load device 740 areelectrically connected to function as diodes. When the third senseamplifier 700 is in a comparing configuration the first PMOS transistor732 is electrically connected to function as a resistor and the firstPMOS transistor 742 is electrically connected to function as a resistorwith the operating points of the first PMOS transistor 732 and thesecond PMOS transistor 742 set to compensate for performance differencesbetween the first load device 730 and the second load device 740 bykeeping the gate voltage of the first PMOS transistor 732 at a biasvoltage VB732 and the gate voltage of the first PMOS transistor 742 at abias voltage VB742. Additionally, when the initialization signal INIThas a high level and the complementary initialization signal INITB has alow level the first input device 510 provides the inhibit voltage VINHto the first load device 730 and the second input device 520 providesthe inhibit voltage VINH to the second load device 740. Further, whenthe initialization signal INIT has a low level and the complementaryinitialization signal INITB has a high level the first input device 510provides the voltage VGBS(0) on the global bit line GB5(0) to the firstload device 730 and the second input device 520 provides the voltage onthe reference line RL5 to the second load device 740.

The third sense amplifier 700 is initialized to generate the biasvoltage VB732 for setting the operating point of the first PMOStransistor 732 and the bias voltage VB742 for setting the operatingpoint of the first PMOS transistor 742 before comparing the voltageVGBS(0) on the global bit line GB5(0) with the voltage on the referenceline RLS. As shown in FIG. 2B, at the start of initializing the thirdsense amplifier 700, the third sense amplifier 700 is in theinitializing configuration, the initialization signal INIT has a highlevel, the complementary initialization signal INITB has a low level,the sense amplifier enable signal SAEN transitions to a high level, thefirst power on signal PONB transitions to a high level, and the secondpower on signal NON transitions to a low level. During initializing thethird sense amplifier 700, the bias voltage VB732 for setting theoperating point for the first PMOS transistor 732 of the first loaddevice 730 is generated and the bias voltage VB742 for setting theoperating point for the first PMOS transistor 742 of the second loaddevice 740 is generated.

The bias voltage VB732 is generated on the first line L737 and thesecond line L738 of the first load device 730 and the bias voltage VB742is generated on the first line L747 and the second line L748 of thesecond load device 740. The voltage on the first line L737 and thevoltage on the second line L738 of the first load device 730 aregenerally the same voltage because turning on the second NMOS transistor733 and the second PMOS transistor 734 electrically connects the firstPMOS transistor 732 to function as a diode by electrically connectingthe first line L737 and the second line L738. The voltage on the firstline L747 and the voltage on the second line L748 of the second loaddevice 740 are generally the same voltage because turning on the secondNMOS transistor 743 and the second PMOS transistor 744 electricallyconnects the first PMOS transistor 742 as to function as a diode byelectrically connecting the first line L747 and the second line L748.The bias voltage VB732 is based on an amount of current flowing throughthe first load device 730 and the bias voltage VB742 is based on anamount of current flowing through the second load device 740. The sum ofthe amount of current flowing through the first load device 730 and theamount of current flowing through the second load device 740 is equal toan amount of current sunk by the current source 750.

A current path through the first load device 730 is created byelectrically connecting the first NMOS transistor 731 and the first PMOStransistor 732 to function as diodes. The first NMOS transistor 731 iselectrically connected to function as a diode by turning on the thirdNMOS transistor 737. The first PMOS transistor 732 is electricallyconnected to function as a diode by turning on the second NMOStransistor 733 and the second PMOS transistor 734. The second NMOStransistor 733 and the third NMOS transistor 737 are turned on becausethe initialization signal INIT has a high level. The second PMOStransistor 734 is turned on because the complementary initializationsignal INITB has a low level. Additionally, the voltage on the firstline L737 is provided to the drain terminal and the source terminal ofthe capacitor connected NMOS transistor 738 by turning on the third NMOStransistor 737 and the inhibit voltage VINH is provided to the gateterminal of the capacitor connected NMOS transistor 738 by turning offthe first PMOS transistor 512 of the first input device 510 and turningon the second PMOS transistor 514 of the first input device 510. Thefirst PMOS transistor 512 is turned off because the initializationsignal INIT has a high level and the second PMOS transistor 514 isturned on because the complementary initialization signal INITB has alow level.

A current path through the second load device 740 is created byelectrically connecting the first NMOS transistor 741 and the first PMOStransistor 742 to function as diodes. The first NMOS transistor 741 iselectrically connected to function as a diode by turning on the thirdNMOS transistor 747. The first PMOS transistor 742 is electricallyconnected to function as a diode by turning on the second NMOStransistor 743 and the second PMOS transistor 744. The second NMOStransistor 743 and the third NMOS transistor 747 are turned on becausethe initialization signal INIT has a high level. The second PMOStransistor 744 is turned on because the complementary initializationsignal INITB has a low level. Additionally, the voltage on the firstline L747 is provided to the drain terminal and the source terminal ofthe capacitor connected NMOS transistor 748 by turning on the third NMOStransistor 747 and the inhibit voltage VINH is provided to the gateterminal of the capacitor connected NMOS transistor 748 by turning offthe first PMOS transistor 522 of the second input device 520 and turningon the second PMOS transistor 524 of the second input device 520. Thefirst PMOS transistor 522 is turned off because the initializationsignal INIT has a high level and the second PMOS transistor 524 isturned on because the complementary initialization signal INITB has alow level.

The first voltage swing limiter 710 and the second voltage swing limiter720 limit the voltage difference between the bias voltage VB732 and thebias voltage VB742. The first voltage swing limiter 710 receives thebias voltage VB732 from the first load device 730 and outputs a voltagebased on the bias voltage VB732 to the second load device 740. Thevoltage output by the first voltage swing limiter 710 generallyincreases when the bias voltage VB732 increases and generally decreaseswhen the bias voltage VB732 decreases. The second voltage swing limiter720 receives the bias voltage VB742 from the second load device 740 andoutputs a voltage based on the bias voltage VB742 to the first loaddevice 730. The voltage output by the second voltage swing limiter 720generally increases when the bias voltage VB742 increases and generallydecreases when the bias voltage VB742 decreases.

The first capacitor connected PMOS transistor 735 and the secondcapacitor connected PMOS transistor 736 of the first load device 730 arecharged to the bias voltage VB732 because the first capacitor connectedPMOS transistor 735 and the second capacitor connected PMOS transistor736 are electrically connected to the second line L738. The bias voltageVB732 on the first line L737 and the second line L738 is approximatelyequal to the voltage on the drain terminal of the first PMOS transistor732. The first capacitor connected PMOS transistor 745 and the secondcapacitor connected PMOS transistor 746 of the second load device 740are charged to the bias voltage VB742 because the first capacitorconnected PMOS transistor 745 and the second capacitor connected PMOStransistor 746 are electrically connected to the second line L748. Thebias voltage VB742 on the first line L747 and the second line L748 isapproximately equal to the voltage on the drain terminal of the firstPMOS transistor 742.

The impact of noise and voltage offsets on the bias voltage VB732 andthe bias voltage VB742 are reduced because the first capacitor connectedPMOS transistor 735 of the first load device 730 and the first capacitorconnected PMOS transistor 745 of the second load device 740 are crosscoupled so that noise and voltage offsets on line L737 and line L738 ofthe first load device 730 are similar to noise and voltage offsets online L747 and line L748 of the second load device 740. Additionally, theimpact of noise and voltage offsets on the bias voltage VB732 and thebias voltage VB742 are reduced because the first coupling canceller 780and the second coupling canceller 790 are cross coupled so that noiseand voltage offsets on line L737 and line L738 of the first load device730 are similar to noise and voltage offsets on line L747 and line L748of the second load device 740.

The impact of voltage transients on the bias voltage VB732 and the biasvoltage VB742 are reduced by the voltage levels of the initializationsignal INIT and the complementary initialization signal INITB beingoffset. Voltage transients introduced through gate to channelcapacitance of the second NMOS transistor 733 by turning on and off thesecond NMOS transistor 733 and voltage transients introduced throughgate to channel capacitance of the second PMOS transistor 734 by turningon and off the second PMOS transistor 734 are offset because the voltagelevels of the initialization signal INIT and the complementaryinitialization signal INITB are offset. Thus, voltage transientsintroduced through gate to channel capacitance of the second NMOStransistor 733 by turning on and off the second NMOS transistor 733 andvoltage transients introduced through gate to channel capacitance of thesecond PMOS transistor 734 by turning on and off the second PMOStransistor 734 at least partially cancel each other because the voltagetransients are offset. Voltage transients introduced through gate tochannel capacitance of the second NMOS transistor 743 by turning on andoff the second NMOS transistor 743 and voltage transients introducedthrough gate to channel capacitance of the second PMOS transistor 744 byturning on and off the second PMOS transistor 744 are offset because thevoltage levels of the initialization signal INIT and the complementaryinitialization signal INITB are offset. Thus, voltage transientsintroduced through gate to channel capacitance of the second NMOStransistor 743 by turning on and off the second NMOS transistor 743 andvoltage transients introduced through gate to channel capacitance of thesecond PMOS transistor 744 by turning on and off the second PMOStransistor 744 at least partially cancel each other because the voltagetransients are offset.

After initializing the third sense amplifier 700 to generate the biasvoltage VB732 and the bias voltage VB742, the third sense amplifier 700compares the voltage VGB5(0) on the global bit line GB5(0) with thevoltage on the reference line RL5. The first PMOS transistor 732 iselectrically connected to function as a resistor with the gate voltageof the first PMOS transistor 732 kept at the bias voltage VB732 and thefirst PMOS transistor 742 is electrically connected to function as aresistor with the gate voltage of the first PMOS transistor 742 kept atthe bias voltage VB742. Keeping the gate voltage of the first PMOStransistor 732 at the bias voltage VB732 and the gate voltage of thefirst PMOS transistor 742 at the bias voltage VB742 increases theaccuracy of comparing the voltage VGB5(0) on the global bit line GB5(0)with the voltage on the reference line RL5 because keeping the gatevoltage of the first PMOS transistor 732 at the bias voltage VB732 andthe gate voltage of the first PMOS transistor 742 at the bias voltageVB742 compensates for performance differences between the first loaddevice 730 and the second load device 740.

As shown in FIG. 2B, at the start of comparing the voltage VGB5(0) onthe global bit line GB5(0) with the voltage on the reference line RL5,the initialization signal INIT transitions to a low level, thecomplementary initialization signal INITB transitions to a high level,the sense amplifier enable signal SAEN has high level, the first poweron signal PONB has a high level, and the second power on signal NON hasa low level. As discussed above, when the initialization signal INIT hasa low level and the complementary initialization signal INITB has a highlevel, the third sense amplifier 700 is in a comparing configuration,the first input device 510 provides the voltage VGB5(0) on the globalbit line GB5(0) to the first load device 730, and the second inputdevice 520 provides the voltage on the reference line RL5 to the secondload device 740. During comparing the voltage VGB5(0) on the global bitline GB5(0) with the voltage on the reference line RL5, a voltage VS737is generated on the first line L737 of the first load device 730 and avoltage VS747 is generated on the first line L747 of the second loaddevice 740 with the voltage VS737 and the voltage VS747 being indicativeof a difference between the voltage VGB5(0) on the global bit lineGB5(0) and the voltage on the reference line RL5. The voltage VS737 isbased on an amount of current flowing through the first load device 730and the voltage VS747 is based on an amount of current flowing throughthe second load device 740. The sum of the amount of current flowingthrough the first load device 730 and the amount of current flowingthrough the second load device 740 is equal to an amount of current sunkby the current source 750.

A current path through the first load device 730 is created by keepingthe gate voltage of first PMOS transistor 732 at the bias voltage VB732and providing the voltage VGB5(0) on the global bit line GB5(0) to thegate terminal of the capacitor connected NMOS transistor 738 so that adifferential signal indicative of a resistive state of resistive changeelement O01 is passed to the gate terminal of the first NMOS transistor731. The differential signal is the voltage on the global bit lineGB5(0) minus the bias voltage VB732 stored voltage on the capacitorconnected NMOS transistor 738. The gate voltage of the first PMOStransistor 732 is kept at the bias voltage VB732 by disconnecting thefirst line L737 from the second line L738 with the first capacitorconnected PMOS transistor 735 and the second capacitor connected PMOStransistor 736 charged to the bias voltage VB732. After disconnectingthe first line L737 from the second line L738 the voltage on the secondline L738 and the gate voltage of the first PMOS transistor 732 are keptat the bias voltage VB732 by the first capacitor connected PMOStransistor 735 and the second capacitor connected PMOS transistor 736.The first line L737 is disconnected from the second line L738 by turningoff the second NMOS transistor 733 and the second PMOS transistor 734.The voltage VGBS(0) on the global bit line GB5(0) is provided to thegate terminal of the capacitor connected NMOS transistor 738 by turningon the first PMOS transistor 512 of the first input device 510 andturning off the second PMOS transistor 514 of the first input device510. The voltage VGBS(0) on the global bit line GB5(0) is driven to avoltage indicative of a resistive state of the resistive change elementO01 as discussed above with respect to generating a voltage indicativeof a resistive state of the resistive change element O01. The secondNMOS transistor 733 of the first load device 730 is turned off and thefirst PMOS transistor 512 of the first input device 510 is turned onbecause the initialization signal INIT has a low level. The second PMOStransistor 734 of the first load device 730 and the second PMOStransistor 514 of the first input device 510 are turned off because thecomplementary initialization signal INITB has a high level.

A current path through the second load device 740 is created by keepingthe gate voltage of first PMOS transistor 742 at the bias voltage VB742and providing the voltage reference line RL5 to the gate terminal of thecapacitor connected NMOS transistor 748 so that voltage on the gateterminal of the first NMOS transistor 741 is the inhibit voltage minusbias voltage stored on the capacitor connected NMOS transistor 748. Thegate voltage of the first PMOS transistor 742 is kept at the biasvoltage VB742 by disconnecting the first line L747 from the second lineL748 with the first capacitor connected PMOS transistor 745 and thesecond capacitor connected PMOS transistor 746 charged to the biasvoltage VB742. After disconnecting the first line L747 from the secondline L748 the voltage on the second line L748 and the gate voltage ofthe first PMOS transistor 742 are kept at the bias voltage VB742 by thefirst capacitor connected PMOS transistor 745 and the second capacitorconnected PMOS transistor 746. The first line L747 is disconnected fromthe second line L748 by turning off the second NMOS transistor 743 andthe second PMOS transistor 744. The voltage on the reference line RL5 isprovided to the gate terminal of the capacitor connected NMOS transistor748 of the second load device 740 by turning on the first PMOStransistor 522 of the second input device 520 and turning off the secondPMOS transistor 524 of the second input device 520. The voltage on thereference line RL5 is driven to the inhibit voltage VINH by turning onthe second NMOS transistor 122 in the reference line connection circuit120 and the second NMOS transistor 122 may be turned on as part ofpreparing the exemplary implementation of the second exemplaryarchitecture for determining a resistive state of the resistive changeelement O01 as discussed above. The second NMOS transistor 743 of thesecond load device 740 is turned off and the first PMOS transistor 522of the second input device 510 is turned on because the initializationsignal INIT has a low level. The second PMOS transistor 744 of thesecond load device 740 and the second PMOS transistor 524 of the secondinput device 520 are turned off because the complementary initializationsignal INITB has a high level.

The amount of current flowing through the first load device 730 and theamount of current flowing through the second load device 740 generallychange when the voltage VGBS(0) on the global bit line GB5(0) changesbecause the voltage on the reference line RL5 is the inhibit voltageVINH and the inhibit voltage VINH is generally the same for READoperations. When the voltage VGB5(0) on the global bit line GB5(0)increases, the amount of current flowing through the first load device730 increases, the amount of current flowing through the second loaddevice 740 decreases, the voltage VS737 on the first line L737 of thefirst load device 730 decreases, and the voltage VS747 on the first lineL747 of the second load device 740 increases. When the voltage VGB5(0)on the global bit line GB5(0) decreases, the amount of current flowingthrough first load device 730 decreases, the amount of current flowingthrough the second load device 740 increases, the voltage VS737 on thefirst line L737 of the first load device 730 increases, and the voltageVS747 on the first line L747 of the second load device 740 decreases.

The difference between the voltage VS737 on the first line L737 in thefirst load device 730 and the voltage VS747 on the first line L747 inthe second load device 740 is indicative of a resistive state of theresistive change element O01. When the resistive change element O01 hasa low resistive state, the voltage VGB5(0) on the global bit line GB5(0)is greater than the inhibit voltage VINH, the amount of current flowingthrough the first load device 730 is greater than the amount of currentflowing through the second load device 740 and the voltage VS737 onfirst line L737 of the first load device 730 is less than the voltageVS747 on the first line L747 of the second load device 740. When theresistive change element O01 has a high resistive state, the voltageVGB5(0) on the global bit line GB5(0) is less than the inhibit voltageVINH, the amount of current flowing through the first load device 730 isless than the amount of current flowing through the second load device740 and the voltage VS737 on first line L737 of the first load device730 is greater than the voltage VS747 on the first line L747 of thesecond load device 740.

The first voltage swing limiter 710 and the second voltage swing limiter720 limit the voltage difference between the voltage VS737 generated onthe first line L737 of the first load device 730 and the voltage VS747generated on the first line L747 of the second load device 740. Thefirst voltage swing limiter 710 receives the voltage VS737 from thefirst load device 730 and outputs a voltage based on the voltage VS737to the second load device 740. The voltage output by the first voltageswing limiter 710 generally increases when the voltage VS737 increasesand generally decreases when the voltage VS737 decreases. The secondvoltage swing limiter 720 receives the voltage VS747 from the secondload device 740 and outputs a voltage based on the voltage VS747 to thefirst load device 730. The voltage output by the second voltage swinglimiter 720 generally increases when the voltage VS747 increases andgenerally decreases when the voltage VS747 decreases. Additionally, theimpact of noise and voltage offsets on the voltage VS737 and the voltageVS747 are reduced because the first coupling canceller 780 and thesecond coupling canceller 790 are cross coupled so that noise andvoltage offsets on line L737 of the first load device 730 are similar tonoise and voltage offsets on line L747 of the second load device 740.

While the first power on signal PONB has a high level, the power controldevice 760 provides the voltage VS737 to the first output 701, the gateterminal of the second PMOS transistor 776 of the latch device 770, andthe gate terminal of the second NMOS transistor 778 of the latch device770 because the second NMOS transistor 767 of the power control device760 is turned on. Also, while the first power on signal PONB has a highlevel, the power control device 760 provides the voltage VS747 to thesecond output 702, the gate terminal of the first PMOS transistor 772 ofthe latch device 770, and the gate terminal of the first NMOS transistor774 of the latch device 770 because the third NMOS transistor 768 of thepower control device 760 is turned on. When resistive change element O01has a low resistive state, the voltage VS737 has a voltage level lessthan a voltage level of the voltage VS747, the gate voltage of the firstPMOS transistor 772 is greater than the gate voltage of the second PMOStransistor 776 and the first PMOS transistor 772 is turned on less thanthe second PMOS transistor 776. Additionally, when resistive changeelement O01 has a low resistive state, the gate voltage of the firstNMOS transistor 774 is greater than the gate voltage of the second NMOStransistor 778 and the first NMOS transistor 774 is turned on greaterthan the second NMOS transistor 778. When resistive change element O01has a high resistive state, the voltage VS737 has a voltage levelgreater than a voltage level of the voltage VS747, the gate voltage ofthe first PMOS transistor 772 is less than the gate voltage of thesecond PMOS transistor 776 and the first PMOS transistor 772 is turnedon greater than the second PMOS transistor 776. Additionally, when theresistive change element O01 has a high resistive state, the gatevoltage of the first NMOS transistor 774 is less than the gate voltageof the second NMOS transistor 778 and the first NMOS transistor 774 isturned on less than the second NMOS transistor 778. During comparing thevoltage VGB5(0) on the global bit line GB5(0) with the voltage on thereference line RL5, current generally does not flow through the latchdevice 770 because the first PMOS transistor 762 of the power controldevice 760 and the first NMOS transistor 764 of the power control device760 are turned off. The first PMOS transistor 762 of the power controldevice 760 is turned off because the first power on signal PONB has ahigh level and the first NMOS transistor 764 of the power control device760 is turned off because the second power on signal NON has a lowlevel.

As shown in FIG. 2B, at the conclusion of comparing the voltage VGB5(0)on the global bit line GB5(0) with the voltage on the reference lineRL5, the initialization signal INIT transitions to a low level, thecomplementary initialization signal INITB transitions to a high level,the sense amplifier enable signal SAEN transitions to a low level, thefirst power on signal PONB transitions to a low level, and after a smalldelay the second power on signal NON transitions to a high level. Asdiscussed above, when the initialization signal INIT has a high leveland the complementary initialization signal INITB has a low level, thethird sense amplifier 700 is in an initializing configuration, the firstinput device 510 provides the inhibit voltage VINH to the first loaddevice 630, and the second input device 520 provides the inhibit voltageVINH to the second input device 640. Additionally, when the first poweron signal PONB has a low level, the latch device 770 is disconnectedfrom the first load device 730 and the second load device 740 and thelatch device 770 is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies thesystem voltage VDD. The latch device 770 is disconnected from the firstload device 730 by turning off the second NMOS transistor 767 of thepower control device 760 and the latch device 770 is disconnected fromthe second load device 740 by turning off the third NMOS transistor 768.The latch device 770 is electrically connected to a power supply, avoltage source, a driver circuit, or other device that supplies thesystem voltage VDD by turning on the PMOS transistor 762 of the powercontrol device 760. The PMOS transistor 762 is turned on, the secondNMOS transistor 667 is turned off, and the third NMOS transistor 768 isturned off because the first power on signal PONB has a low level.Further, when the second power on signal NON has a high level, the latchdevice 770 is in electrical communication with a power supply, a voltagesource, a driver circuit, or other device that supplies 0 volts orground. The latch device 770 is electrically connected to the powersupply, the voltage source, the driver circuit, or other device thatsupplies the 0 volts or ground by turning on the first NMOS transistor764 of the power control device 760. The first NMOS transistor 764 isturned on because the second power on signal NON has a high level.

When comparing the voltage VGB5(0) on the global bit line GB5(0) withthe voltage on the reference line RL5 concludes, the voltage on thefirst output 701, the voltage on the gate terminal of the second PMOStransistor 776, and the voltage on the gate terminal of the second NMOStransistor 778 are approximately equal to the voltage VS737 and thevoltage on the second output 702, the voltage on the gate terminal ofthe first PMOS transistor 772, and the voltage on the gate terminal ofthe first NMOS transistor 774 are approximately equal to the voltageVS747. The voltage difference between the voltage VS737 and the voltageVS747 can be increased by having a small delay between the first poweron signal PONB transitioning to a low level and the second power onsignal NON transitioning to high level. During the small delay, currentcan flow from the power supply, the voltage source, the driver circuit,or other device that supplies the system voltage VDD through the PMOStransistor 762 of the power control device 760 and the first PMOStransistor 772 of the latch device 770 and pull up the voltages on thefirst output 701, the gate terminal of the second PMOS transistor 776,and the gate terminal of the second NMOS transistor 778. Also, duringthe small delay, current can flow from the power supply, the voltagesource, the driver circuit, or other device that supplies the systemvoltage VDD through the PMOS transistor 762 of the power control device760 and the second PMOS transistor 776 of the latch device 770 and pullup the voltages on the second output 702, the gate terminal of the firstPMOS transistor 772, and the gate terminal of the first NMOS transistor774. When the voltage level of the voltage VS737 is less than thevoltage level of the voltage VS747, the first PMOS transistor 772 isturned on less than the second PMOS transistor 776 and the voltages onthe first output 701, the gate terminal of the second PMOS transistor776, and the gate terminal of the second NMOS transistor 778 are pulledup less than the voltages on the second output 702, the gate terminal ofthe first PMOS transistor 772, and the gate terminal of the first NMOStransistor 774 because an amount of current flowing through the firstPMOS transistor 772 is less than an amount of current flowing throughthe second PMOS transistor 776. When the voltage level of the voltageVS737 is greater than the voltage level of the voltage VS747, the firstPMOS transistor 772 is turned on greater than the second PMOS transistor776 and the voltages on the first output 701, the gate terminal of thesecond PMOS transistor 776, and the gate terminal of the second NMOStransistor 778 are pulled up greater than the voltages on the secondoutput 702, the gate terminal of the first PMOS transistor 772, and thegate terminal of the first NMOS transistor 774 because an amount ofcurrent flowing through the first PMOS transistor 772 is greater than anamount of current flowing through the second PMOS transistor 776.Alternatively, the first power on signal PONB transitioning to a lowlevel and the second power on signal NON transitioning to a high levelcan occur at approximately the same time.

After the first power on signal PONB has a low level and the secondpower on signal NON has a high level, the voltages on the first output701, the gate terminal of the second PMOS transistor 776, and the gateterminal of the second NMOS transistor 778 transition to the systemvoltage VDD or 0 volts or ground and the voltages on the second output702, the gate terminal of the first PMOS transistor 772, and the gateterminal of the first NMOS transistor 774 transition to the systemvoltage VDD or 0 volts or ground. When the resistive change element O01has a low resistive state the voltage on the first output 701, the gateterminal of the second PMOS transistor 776, and the gate terminal of thesecond NMOS transistor 778 transition to 0 volts or ground and thevoltages on the second output 702, the gate terminal of the first PMOStransistor 772, and the gate terminal of the first NMOS transistor 774transition to the system voltage VDD because the first PMOS transistor772 is turned on less than the second PMOS transistor 776 and the firstNMOS transistor 774 is turned on greater than the second NMOS transistor778. The voltage on the first output 701 being 0 volts or ground and thevoltage on the second output 702 being the system voltage VDD is storedin the latch device 770 by the first PMOS transistor 772 being turnedoff, the first NMOS transistor 774 being turned on, the second PMOStransistor 776 being turned on, and the second NMOS transistor 778 beingturned off. Additionally, the voltage on the first output 701 isgenerally kept at 0 volts or ground and the voltage on the second output702 is generally kept at the system voltage VDD by the first PMOStransistor 772 being turned off, the first NMOS transistor 774 beingturned on, the second PMOS transistor 776 being turned on, and thesecond NMOS transistor 778 being turned off. Therefore, when resistivechange element O01 has a low resistive state the third sense amplifier700 outputs 0 volts or ground on the first output 701 and the systemvoltage VDD on the second output 702.

When the resistive change element O01 has a high resistive state thevoltage on the first output 701, the gate terminal of the second PMOStransistor 776, and the gate terminal of the second NMOS transistor 778transition to the system voltage VDD and the voltages on the secondoutput 702, the gate terminal of the first PMOS transistor 772, and thegate terminal of the first NMOS transistor 774 transition to 0 volts orground because the first PMOS transistor 772 is turned on greater thanthe second PMOS transistor 776 and the first NMOS transistor 774 isturned on less than the second NMOS transistor 778. The voltage on thefirst output 701 being the system voltage VDD and the voltage on thesecond output 702 being 0 volts or ground is stored in the latch device770 by the first PMOS transistor 772 being turned on, the first NMOStransistor 774 being turned off, the second PMOS transistor 776 beingturned off, and the second NMOS transistor 778 being turned on.Additionally, the voltage on the first output 701 is generally kept thesystem voltage VDD and the voltage on the second output 702 is generallykept 0 volts or ground by the first PMOS transistor 772 being turned on,the first NMOS transistor 774 being turned off, the second PMOStransistor 776 being turned off, and the second NMOS transistor 778being turned on. Therefore, when resistive change element O01 has a highresistive state the third sense amplifier 700 outputs the system voltageVDD on the first output 701 and 0 volts or ground on the second output702.

Referring now to FIGS. 5F-1, 5F-2, 5F-3, and 5F-4, an exemplary DDRcompatible implementation of the second exemplary architecture forprogramming and accessing resistive change elements is illustrated in asimplified schematic diagram. The exemplary DDR compatibleimplementation of the second exemplary architecture includes a pluralityof global bit lines GB6(0)-GB6(x), a resistive change element array 101having a plurality of sections Section A-Section Z, word line drivercircuitry 110 a-110 z for each section, a reference line RL6, areference line connection circuit 120 a-120 z for each section, aplurality of bus lines BL60-BL6 x, a keeper circuit 130, a resistor 530,a global bit line connection circuit 590, a plurality of write buffercircuits 1500-150 x, a plurality of current sources 1600-160 x, acapacitor 580, a plurality of first input devices 5100-510 x, a secondinput device 5200, and a plurality of sense amplifiers 6000-600 x. Theresistive change element array 101 having a plurality of sectionsSection A-Section Z, the word line driver circuitry 110 a-110 z for eachsection, the reference line connection circuit 120 a-120 z for eachsection, the keeper circuit 130, the plurality of write buffer circuits1500-150 x, and the plurality of current sources 1600-160 x have asimilar structure to the resistive change element array 101 having aplurality of sections Section A-Section Z, the word line drivercircuitry 110 a-110 z for each section, the reference line connectioncircuit 120 a-120 z for each section, the keeper circuit 130, theplurality of write buffer circuits 1500-150 x, and the plurality ofcurrent sources 1600-160 x discussed above with respect to the exemplaryDDR compatible implementation of first exemplary architecture.Therefore, the resistive change element array 101 having a plurality ofsections Section A-Section Z, the word line driver circuitry 110 a-110 zfor each section, the reference line connection circuit 120 a-120 z foreach section, the keeper circuit 130, the plurality of write buffercircuits 1500-150 x, and the plurality of current sources 1600-160 x arenot discussed in detail with respect to the exemplary DDR compatibleimplementation of the second exemplary architecture. Additionally, theresistor 530 and the capacitor 580 have a similar structure to theresistor 530 and the capacitor 580 discussed above with respect to theexemplary implementation of the second exemplary architecture.Therefore, the resistor 530 and the capacitor 580 are not discussed indetail with respect to the exemplary DDR compatible implementation ofthe second exemplary architecture.

The global bit line connection circuit 590 includes a PMOS transistor590 r having a drain terminal, a gate terminal, and a source terminaland a plurality of PMOS transistors 590 g-59 xg having drain terminals,gate terminals, and source terminals. The numbering convention for theplurality of PMOS transistors 590 g-59 xg includes a column number asthe next to last reference character, the numbering convention for theplurality of bus lines BL60-BL6 x includes a column number as the lastreference character, and the numbering convention for the plurality ofglobal bit lines GB6(0)-GB6(x) begins with letters and number GB6indicating the line is a global bit line followed by a column number inparentheses. The drain terminal of the PMOS transistor 590 r is inelectrical communication with the second input device 5200. The gateterminal of the PMOS transistor 590 r is in electrical communicationwith control logic, such as a processor, a controller, and amicrocontroller. The source terminal of the PMOS transistor 590 r is inelectrical communication with the reference line RL6 through theresistor 530. The drain terminals of the plurality of PMOS transistors590 g-59 xg are in electrical communication with bus lines BL60-BL6 xhaving the same column numbers. The gate terminals of the plurality ofPMOS transistors 590 g-59 xg are in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller.The source terminals of the plurality of PMOS transistors 590 g-59 xgare in electrical communication with global bit lines GB6(0)-GB6(x)having the same column number. Alternatively, the plurality of PMOStransistors 590 g-59 xg can be other types of field effect transistors,such as carbon nanotube field effect transistors (CNTFETs), SiGE FETs,fully-depleted silicon-on-insulator FETs, or multiple gate field effecttransistors such as FinFETs, and/or the PMOS transistor 590 r can beother types of field effect transistors, such as carbon nanotube fieldeffect transistors (CNTFETs), SiGE FETs, fully-depletedsilicon-on-insulator FETs, or multiple gate field effect transistorssuch as FinFETs. It is noted that when field effect transistors that donot require a semiconductor substrate are used this enables the fieldeffect transistors to be fabricated on insulator material, andadditionally, enables the field effect transistors to be stacked toreduce the amount of chip area consumed by the plurality of PMOStransistors 590 g-59 xg and/or the PMOS transistor 590 r.

The global bit line connection circuit 590 includes the PMOS transistor590 r in electrical communication with the reference line RL6 and thesecond input device 5200 so that the noise behavior of a voltage on thereference line RL6 received by the second input device 5200 is similarto the noise behaviors of voltages on the bus lines BL60-BL6 x receivedby the first input devices 5100-510 x. The PMOS transistor 590 r andplurality of PMOS transistors 590 g-59 xg receive a signal CDO forcontrolling current flow through the PMOS transistor 590 r and theplurality of PMOS transistors 590 g-59 xg. The control logic suppliesthe signal CDO.

Each of the first input devices of the plurality of first input devices5100-510 x has the same structure as the first input device 5100, andthus, the discussion below of the first input device 5100 is applicableto each of the first input devices of the plurality of first inputdevices 5100-510 x. The numbering convention for the plurality of firstinput devices 5100-510 x includes a column number as the last referencecharacter and a first input device corresponds with a global bit linehaving the same column number.

The first input device 5100 includes a first PMOS transistor 5120 havinga drain terminal, a gate terminal, and a source terminal and a secondPMOS transistor 5140 having a drain terminal, a gate terminal, and asource terminal. The drain terminal of the first PMOS transistor 5120 isin electrical communication with a first input terminal of the senseamplifier 5500 having the same column number as the first input device5100, the gate terminal of the first PMOS transistor 5120 is inelectrical communication with control logic, such as a processor, acontroller, and a microcontroller, to receive an initialization signalINIT, and the source terminal of the first PMOS transistor 5120 is inelectrical communication with the bus line BL60 having the same columnnumber as the first input device 5100. The drain terminal of the secondPMOS transistor 5140 is in electrical communication with a first inputterminal of sense amplifier 5500 having the same column number the firstinput device 5100, the gate terminal of the second PMOS transistor 5140is in electrical communication with control logic, such as a processor,a controller, and a microcontroller, to receive a complementaryinitialization signal INITB, and the source terminal of the second PMOStransistor 5140 is in electrical communication with a power supply, avoltage source, a driver circuit, or other device that supplies aninhibit voltage VINH.

The second input device 5200 includes a first PMOS transistor 5220having a drain terminal, a gate terminal, and a source terminal and asecond PMOS transistor 5240 having a drain terminal, a gate terminal,and a source terminal. The drain terminal of the first PMOS transistor5220 is in electrical communication with second input terminals of thesense amplifiers 5500-550 x and the capacitor 580, the gate terminal ofthe first PMOS transistor 5220 is in electrical communication withcontrol logic, such as a processor, a controller, and a microcontroller,to receive an initialization signal INIT, and the source terminal of thefirst PMOS transistor 5220 is in electrical communication with theglobal bit line connection circuit 590. The drain terminal of the secondPMOS transistor 5240 is in electrical communication with second inputterminals of sense amplifiers 5500-550 x and the capacitor 580, the gateterminal of the second PMOS transistor 5240 is in electricalcommunication with control logic, such as a processor, a controller, anda microcontroller, to receive a complementary initialization signalINITB, and the source terminal of the second PMOS transistor 5240 is inelectrical communication with a power supply, a voltage source, a drivercircuit, or other device that supplies an inhibit voltage VINH.

Each sense amplifier of the plurality of sense amplifiers 5500-550 x hasa first input terminal, a second input terminal, and two outputterminals. The numbering convention for the plurality of senseamplifiers 5500-550 x includes a column number as the last referencecharacter and a sense amplifier corresponds with a global bit linehaving the same column number. The first input terminal of each senseamplifier of the plurality of sense amplifiers 5500-550 x is inelectrical communication with the first input device having the samecolumn number as that sense amplifier. The second input terminal of eachsense amplifier of the plurality of sense amplifiers 5500-550 x is inelectrical communication with the second input device 5200 and thecapacitor 580. The two output terminals of each sense amplifier of theplurality of sense amplifiers 5500-550 x can be in electricalcommunication with a bus, a buffer, a level shift circuit, a testcircuit, or control logic such as a processor, a controller, and amicrocontroller. Each sense amplifier of the plurality of senseamplifiers 5500-550 x can be a second sense amplifier 600 discussedabove with respect to FIG. 6 or a third sense amplifier 700 discussedabove with respect to FIG. 7.

The exemplary DDR compatible implementation of the second exemplaryarchitecture shown in FIGS. 5F-1, 5F-2, 5F-3, and 5F-4 provides forPROGRAMMING operations of multiple resistive change elements to the sameresistive state at the same time and READ operations, SET VERIFYoperations, and RESET VERIFY operations of multiple resistive changeelements at the same time. For example, PROGRAMMING operations to adjustresistive states of even resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 can be performed at the same time. For example,PROGRAMMING operations to adjust resistive states of NUM even resistivechange elements in electrical communication with a word line in asection of the resistive change element array 101 can be performed atthe same time, where NUM is a number of resistive change elementsgreater than one and less than the total number of even resistive changeelements in electrical communication with the word line. For example,PROGRAMMING operations to adjust resistive states of odd resistivechange elements in electrical communication with a word line in asection of the resistive change element array 101 can be performed atthe same time. For example, PROGRAMMING operations to adjust resistivestates of NUM odd resistive change elements in electrical communicationwith a word line in a section of the resistive change element array 101can be performed at the same time, where NUM is a number of resistivechange elements greater than one and less than the total number of oddresistive change elements in electrical communication with the wordline. For example, READ operations, SET VERIFY operations, and RESETVERIFY operations of even resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 can be performed at the same time. For example, READoperations, SET VERIFY operations, and RESET VERIFY operations of NUMeven resistive change elements in electrical communication with a wordline in a section of the resistive change element array 101 can beperformed at the same time, where NUM is a number of resistive changeelements greater than one and less than the total number of evenresistive change elements in electrical communication with the wordline. For example, READ operations, SET VERIFY operations, and RESETVERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 can be performed at the same time. For example, READoperations, SET VERIFY operations, and RESET VERIFY operations of NUModd resistive change elements in electrical communication with a wordline in a section of the resistive change element array 101 can beperformed at the same time, where NUM is a number of resistive changeelements greater than one and less than the total number of oddresistive change elements in electrical communication with the wordline.

Additionally, the exemplary DDR compatible implementation of the secondexemplary architecture shown in FIGS. 5F-1, 5F-2, 5F-3, and 5F-4provides for PROGRAMMING operations, READ operations, SET VERIFYoperations, and RESET VERIFY operations of one resistive change elementat a time. For example, PROGRAMMING operations, READ operations, SETVERIFY operations, and RESET VERIFY operations of one resistive changeelement at a time may be performed in a test mode of the exemplary DDRcompatible implementation of the second exemplary architecture.PROGRAMMING operations, READ operations, SET VERIFY operations, andRESET VERIFY operations of one resistive change element at a time in theexemplary DDR compatible implementation of the second exemplaryarchitecture can be performed in a similar manner to PROGRAMMINGoperations, READ operations, SET VERIFY operations, and RESET VERIFYoperations of resistive change elements in the exemplary implementationof the second exemplary architecture shown in FIGS. 5B-1 and 5B-2 anddiscussed above. Therefore, PROGRAMMING operations, READ operations, SETVERIFY operations, and RESET VERIFY operations of one resistive changeelement at a time in the exemplary DDR compatible implementation of thesecond exemplary architecture are not discussed in detail below. It isnoted that the exemplary DDR compatible implementation of the secondexemplary architecture may be used with interface circuitry tailored forother SRAM interfaces so that the exemplary DDR compatibleimplementation of the second exemplary architecture is compatible withother SRAM interfaces.

PROGRAMMING operations of resistive change elements in the exemplary DDRcompatible implementation of the second exemplary architecture shown inFIGS. 5F-1, 5F-2, 5F-3, and 5F-4 are performed in a similar manner toPROGRAMMING operations of resistive change elements in the exemplary DDRcompatible implementation of the first exemplary architecture.PROGRAMMING operations of resistive change elements in the exemplary DDRcompatible implementation of the first exemplary architecture arediscussed above. Therefore, PROGRAMMING operations of resistive changeelements in the exemplary DDR compatible implementation of the secondexemplary architecture shown in FIGS. 5F-1, 5F-2, 5F-3, and 5F-4 are notdiscussed in detail below. READ operations, SET VERIFY operations, andRESET VERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of the resistive changeelement array 101 are discussed below with respect to FIGS. 5G-1, 5G-2,5G-3, and 5G-4 that show current flow during a READ operation of oddresistive change elements in electrical communication with word lineWa(1). It is additionally noted that READ operations, SET VERIFYoperations, and RESET VERIFY operations of odd resistive change elementsin electrical communication with a word line in a section of resistivechange element array 101 and READ operations, SET VERIFY operations, andRESET VERIFY operations of even resistive change elements in electricalcommunication with a word line in a section of resistive change elementarray 101 can be performed in a similar manner to the READ operations,SET VERIFY operations, and RESET VERIFY operations of odd resistivechange elements in electrical communication with word line Wa(1).

Referring now to FIGS. 5G-1, 5G-2, 5G-3, and 5G-4, a READ operation ofodd resistive change elements in electrical communication with word lineWa(1) starts, as similarly discussed above in step 402 of the flow chart400, by providing neutral voltage conditions for the plurality ofresistive change elements E00 a-Oxya in Section A and the plurality ofresistive change elements E00 z-Oxyz in Section Z. The neutral voltageconditions are provided for the plurality of resistive change elementsE00 a-Oxya in section A by floating the plurality of even bit linesBea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x) andapplying the inhibit voltage VINH to the plurality of word linesWa(0)-Wa(y) with the plurality of even bit lines Bea(0)-Bea(x) and theplurality of odd bit lines Boa(0)-Boa(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00 a-Oxya. Floating a linerefers to electrically connecting the line such that a voltage on theline exists due to a line capacitance of the line. The plurality of evenbit lines Bea(0)-Bea(x) are floated by disconnecting the plurality ofeven bit lines Bea(0)-Bea(x) from the plurality of global bit linesGB6(0)-GB6(x) by turning off the plurality of even selection devicesNeaO-Neax in Section A. The plurality of even selection devicesNeaO-Neax are turned off by control logic, such as a processor, acontroller, and a microcontroller, supplying a signal SSELea having alow level. The plurality of odd bit lines Boa(0)-Boa(x) are floated bydisconnecting the plurality of odd bit lines Boa(0)-Boa(x) from theplurality of global bit lines GB6(0)-GB6(x) by turning off the pluralityof odd selection devices NoaO-Noax in Section A. The plurality of oddselection devices NoaO-Noax are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELoa having a low level. It is noted that control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELea having a low level and a signal SSELoa having a low level alsoturns off the first NMOS transistor 121 a and the second NMOS transistor122 a of the reference line connection circuit 120 a for Section A.

The inhibit voltage VINH is applied to the plurality of word linesWa(0)-Wa(y) by the word line driver circuitry 110 a for Section Adriving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110da-11 yda receive the system voltage VDD on the first power terminalsbecause the first NMOS transistor 110 pa is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal S0 a having a high level and receive the inhibit voltage VINH onthe second power terminals because the second NMOS transistor 111 pa isturned on by the control logic supplying the signal S1 a having a highlevel. The plurality of word line driver circuits 110 da-11 yda supplythe inhibit voltage VINH based on the plurality of signals ITE0 a-ITEyasupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sa-11 ysa areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 a-SKya have lowlevels.

Driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating causesvoltages on the plurality of word lines Wa(0)-Wa(y), voltages on theplurality of even bit lines Bea(0)-Bea(x), and voltages on the pluralityof odd bit lines Boa(0)-Boa(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bea(0)-Bea(x)and voltages on the plurality of odd bit lines Boa(0)-Boa(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wa(0)-Wa(y) through the plurality ofresistive change elements E00 a-Oxya into the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x).The inhibit voltage VINH exists on the plurality of even bit linesBea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x) due toline capacitances because the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) are floating. Thus,driving voltages on the plurality of word lines Wa(0)-Wa(y) to theinhibit voltage VINH with the plurality of even bit lines Bea(0)-Bea(x)and the plurality of odd bit lines Boa(0)-Boa(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 a-Oxya.Additionally, driving voltages on the plurality of word linesWa(0)-Wa(y) to the inhibit voltage VINH with the plurality of even bitlines Bea(0)-Bea(x) and the plurality of odd bit lines Boa(0)-Boa(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 a-Oxya to be approximately 0volts.

The neutral voltage conditions are provided for the plurality ofresistive change elements E00 z-Oxyz in section Z by floating theplurality of even bit lines Bez(0)-Bez(x) and the plurality of odd bitlines Boz(0)-Boz(x) and applying the inhibit voltage VINH to theplurality of word lines Wz(0)-Wz(y) with the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) floatingso that voltages approximately equal to the inhibit voltage VINH areapplied to the top electrodes and the bottom electrodes of the resistivechange elements in the plurality of resistive change elements E00z-Oxyz. Floating a line refers to electrically connecting the line suchthat a voltage on the line exists due to a line capacitance of the line.The plurality of even bit lines Bez(0)-Bez(x) are floated bydisconnecting the plurality of even bit lines Bez(0)-Bez(x) from theplurality of global bit lines GB6(0)-GB6(x) by turning off the pluralityof even selection devices Nez0-Nezx in Section Z. The plurality of evenselection devices Nez0-Nezx are turned off by control logic, such as aprocessor, a controller, and a microcontroller, supplying a signalSSELez having a low level. The plurality of odd bit lines Boz(0)-Boz(x)are floated by disconnecting the plurality of odd bit linesBoz(0)-Boz(x) from the plurality of global bit lines GB6(0)-GB6(x) byturning off the plurality of odd selection devices Noz0-Nozx in SectionZ. The plurality of odd selection devices Noz0-Nozx are turned off bycontrol logic, such as a processor, a controller, and a microcontroller,supplying a signal SSELoz having a low level. It is noted that controllogic, such as a processor, a controller, and a microcontroller,supplying a signal SSELez having a low level and a signal SSELoz havinga low level also turns off the first NMOS transistor 121 z and thesecond NMOS transistor 122 z of the reference line connection circuit120 z for Section Z.

The inhibit voltage VINH is applied to the plurality of word linesWz(0)-Wz(y) by the word line driver circuitry 110 z for Section Zdriving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH. The plurality of word line driver circuits 110dz-11 ydz receive the system voltage VDD on the first power terminalsbecause the first NMOS transistor 110 pz is turned on by control logic,such as a processor, a controller, and a microcontroller, supplying thesignal S0 z having a high level and receive the inhibit voltage VINH onthe second power terminals because the second NMOS transistor 111 pz isturned on by the control logic supplying the signal S1 z having a highlevel. The plurality of word line driver circuits 110 dz-11 ydz supplythe inhibit voltage VINH based on the plurality of signals ITE0 z-ITEyzsupplied by control logic, such as a processor, a controller, and amicrocontroller. The plurality of sink transistors 110 sz-11 ysz areturned off because control logic, such as a processor, a controller, anda microcontroller, supplies the plurality of signals SK0 z-SKyz have lowlevels.

Driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating causesvoltages on the plurality of word lines Wz(0)-Wz(y), voltages on theplurality of even bit lines Bez(0)-Bez(x), and voltages on the pluralityof odd bit lines Boz(0)-Boz(x) to be approximately equal to the inhibitvoltage VINH. Voltages on the plurality of even bit lines Bez(0)-Bez(x)and voltages on the plurality of odd bit lines Boz(0)-Boz(x) areapproximately equal to the inhibit voltage VINH because currents flowfrom the plurality of word lines Wz(0)-Wz(y) through the plurality ofresistive change elements E00 z-Oxyz into the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x).The inhibit voltage VINH exists on the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) due toline capacitances because the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) are floating. Thus,driving voltages on the plurality of word lines Wz(0)-Wz(y) to theinhibit voltage VINH with the plurality of even bit lines Bez(0)-Bez(x)and the plurality of odd bit lines Boz(0)-Boz(x) floating results inapplication of voltages approximately equal to the inhibit voltage VINHto the top electrodes and the bottom electrodes of the resistive changeelements in the plurality of resistive change elements E00 z-Oxyz.Additionally, driving voltages on the plurality of word linesWz(0)-Wz(y) to the inhibit voltage VINH with the plurality of even bitlines Bez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x)floating causes the voltages across resistive change elements in theplurality of resistive change elements E00 z-Oxyz to be approximately 0volts.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 404 of the flow chart 400, by biasing theplurality of global bit lines GB6(0)-GB6(x). The plurality of global bitlines GB6(0)-GB6(x) are biased to the inhibit voltage VINH by floatingthe plurality of global bit lines GB6(0)-GB6(x) and applying the inhibitvoltage VINH to the plurality of global bit lines GB6(0)-GB6(x). Theplurality of global bit lines GB6(0)-GB6(x) are floated by disconnectingthe plurality of global bit lines GB6(0)-GB6(x) from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A, the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z, and the plurality of bus lines BL60-BL6 x. The plurality ofglobal bit lines GB6(0)-GB6(x) may be disconnected from the plurality ofeven bit lines Bea(0)-Bea(x) and the plurality of odd bit linesBoa(0)-Boa(x) in Section A as part of providing neutral voltageconditions for the plurality of resistive change elements E00 a-Oxya inSection A as discussed above. The plurality of global bit linesGB6(0)-GB6(x) may be disconnected from the plurality of even bit linesBez(0)-Bez(x) and the plurality of odd bit lines Boz(0)-Boz(x) inSection Z as part of providing neutral voltage conditions for theplurality of resistive change elements E00 z-Oxyz in Section Z asdiscussed above. The plurality of global bit lines GB6(0)-GB6(x) aredisconnected from the plurality of bus lines BL60-BL6 x by turning offthe plurality of PMOS transistors 590 g-59 xg in the global bit lineconnection circuit 590. The plurality of PMOS transistors 590 g-59 xgare turned off by control logic, such as a processor, a controller, anda microcontroller, supplying a signal CDO having a high level. Theinhibit voltage VINH is applied to the plurality of global bit linesGB6(0)-GB6(x) by electrically connecting the plurality of global bitlines GB6(0)-GB6(x) to a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH byturning on the plurality of NMOS transistors 130 k-13 xk in the keepercircuit 130. The plurality of NMOS transistors 130 k-13 xk are turned onby control logic, such as a processor, a controller, and amicrocontroller, supplying a signal KEEPe having a high level and asignal KEEPo having a high level. It is noted that control logic, suchas a processor, a controller, and a microcontroller, supplying a signalCDO having a high level also turns off the PMOS transistor 590 r in theglobal bit line connection circuit 590. It is further noted that thereference line RL6 floats because the PMOS transistor 590 r, the firstNMOS transistor 121 a and the second NMOS transistor 122 a of thereference line connection circuit 120 a for Section A, and the firstNMOS transistor 121 z and the second NMOS transistor 122 z of thereference line connection circuit 120 z for Section Z are turned off.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A proceeds, as similarlydiscussed above in step 406 of the flow chart 400, by selecting the oddresistive change elements O01 a, Ox1 a in electrical communication withword line Wa(1) in Section A from the plurality of resistive changeelements E00 a-Oxya in Section A and the plurality of resistive changeelements E00 z-Oxyz in Section Z. The odd resistive change elements O01a, Ox1 a in electrical communication with word line Wa(1) in Section Aare selected from the plurality of resistive change elements E00 a-Oxyain Section A and the plurality of resistive change elements E00 z-Oxyzin Section Z by control logic, such as a processor, a controller, and amicrocontroller. The resistive change elements E00 a-Ox0 a, E01 a, Ex1a, and E0 ya-Oxya in the plurality of resistive change elements E00a-Oxya in Section A and the plurality of resistive change elements E00z-Oxyz in Section Z that are not selected are referred to as unselectedresistive change elements.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 408 of the flow chart 400, by preparing theexemplary DDR compatible implementation of the second exemplaryarchitecture for determining resistive states of the odd resistivechange elements O01 a, Ox1 a. The exemplary DDR compatibleimplementation of the second exemplary architecture is prepared fordetermining resistive states of the odd resistive change elements O01 a,Ox1 a by changing electrical connections of the reference line RL6,driving the voltage on the reference line RL6 to the inhibit voltageVINH, changing electrical connections of the plurality of odd bit linesBoa(0)-Boa(x), changing electrical connections of the plurality ofglobal bit lines GB6(0)-GB6(0), and disconnecting a power supply, avoltage source, a driver circuit, or the device that supplies theinhibit voltage VINH from the plurality of global bit linesGB6(0)-GB6(x). The electrical connections of the reference line RL6 arechanged so that the reference line RL6 is in electrical communicationwith the second input device 5200. The reference line RL6 iselectrically connected to the second input device 5200 by turning on thePMOS transistor 590 r. The PMOS transistor 590 r is turned on by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal CDO having a low level. The voltage on the referenceline RL6 is driven to the inhibit voltage VINH by electricallyconnecting the reference line RL6 through the second NMOS transistor 122a of the reference line connection circuit 120 a and the second NMOStransistor 111 pa of the word line driver circuit 110 a to a powersupply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH. The second NMOS transistor 122 a isturned on by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELoa having a high level and, asdiscussed above with respect to providing neutral voltage conditions forthe plurality of resistive change elements E00 a-Oxya in Section A andthe plurality of resistive change elements E00 z-Oxyz in Section Z, thesecond NMOS transistor 111 pa of the word line driver circuit 110 a isturned on.

The electrical connections of the plurality of odd bit linesBoa(0)-Boa(x) and the electrical connections of the plurality of globalbit lines GB6(0)-GB6(x) are changed and a power supply, a voltagesource, a driver circuit, or other device that supplies the inhibitvoltage VINH is disconnected from the plurality of global bit linesGB6(0)-GB6(x) so that voltages indicative of the resistive states of theodd resistive change elements O01 a, Ox1 a can be generated on theplurality of odd bit lines Boa(0)-Boa(x), the plurality of global bitlines GB6(0)-GB6(x), and the plurality of bus lines BL60-BL6 x. Theelectrical connections of the plurality of odd bit lines Boa(0)-Boa(x)are changed so that the plurality of odd bit lines Boa(0)-Boa(x) are inelectrical communication with the plurality of global bit linesGB6(0)-GB6(x). The plurality of odd bit lines Boa(0)-Boa(x) areelectrically connected to the plurality of global bit linesGB6(0)-GB6(x) by turning on the plurality of odd selection devicesNoa0-Noax. The plurality of odd selection devices Noa0-Noax are turnedon by control logic, such as a processor, a controller, and amicrocontroller, supplying a signal SSELo having a high level. Theplurality of odd bit lines Boa(0)-Boa(x) may be electrically connectedto the plurality of global bit lines GB6(0)-GB6(x) as part of drivingthe voltage on the reference line RL6 to the inhibit voltage VINH asdiscussed above.

The electrical connections of the plurality of global bit linesGB6(0)-GB6(x) are changed so that the plurality of global bit linesGB6(0)-GB6(x) are in electrical communication with the plurality of oddbit lines Boa(0)-Boa(x) and the plurality of bus lines BL60-BL6 x. Theplurality of global bit lines GB6(0)-GB6(x) are electrically connectedto the plurality of odd bit lines Boa(0)-Boa(x) by turning on theplurality of odd selection devices Noa0-Noax as discussed above and theplurality of global bit lines GB6(0)-GB6(x) may be electricallyconnected to the plurality of odd bit lines Boa(0)-Boa(x) as part ofdriving the voltage on the reference line RL6 to the inhibit voltageVINH as discussed above. The plurality of global bit lines GB6(0)-GB6(x)are electrically connected to the plurality of bus lines BL60-BL6 x byturning on the plurality of PMOS transistors 590 g-59 xg. The pluralityof PMOS transistors 590 g-59 xg are turned on by control logic, such asa processor, a controller, and a microcontroller, supplying a signal CDOhaving a low level. The plurality of global bit lines GB6(0)-GB6(x) maybe electrically connected to the plurality of bus lines BL60-BL6 x aspart of electrically connecting the reference line RL6 to the secondinput device 5200 as discussed above. A power supply, a voltage source,a driver circuit, or other device that supplies the inhibit voltage VINHis disconnected from the plurality of global bit lines GB6(0)-GB6(x) byturning off the plurality of NMOS transistors 130 k-13 xk. The pluralityof NMOS transistors 130 k-13 xk are turned off by control logic, such asa processor, a controller, and a microcontroller, supplying a signalKEEPe having a low level and a signal KEEPo having a low level.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 410 of the flow chart 400, by generatingvoltages indicative of resistive states of the odd resistive changeelements O01 a, Ox1 a. Voltages indicative of resistive states of theodd resistive change elements O01 a, Ox1 a are generated on theplurality of odd bit lines Boa(0)-Boa(x), the plurality of global bitlines GB6(0)-GB6(x), and the plurality of bus lines BL60-BL6 x bydriving the voltage on the word line Wa(1) to the system voltage VDD andsinking an amount of current for a READ operation from each bus line ofthe plurality the bus lines BL60-BL6 x. As discussed above, providingneutral voltage conditions for the plurality of resistive changeelements E00 a-Oxya causes voltages on the plurality of word linesWa(0)-Wa(y), voltages on the plurality of even bit lines Bea(0)-Bea(x),and voltages on the plurality of odd bit lines Boa(0)-Boa(x) to beapproximately equal to the inhibit voltage VINH. Also, as discussedabove, the plurality of global bit lines GB6(0)-GB6(x) are biased to theinhibit voltage VINH. Thus, for generating voltages indicative ofresistive states of the odd resistive change elements OO1 a, Ox1 a, avoltage on the word line Wa(1) transitions from the inhibit voltage VINHto the system voltage VDD and the voltages on the plurality of odd bitlines Boa(0)-Boa(x) and the plurality of global bit lines GB6(0)-GB6(x)transition from the inhibit voltage VINH to voltages indicative ofresistive states of the odd resistive change elements OO1 a, Ox1 a.

The voltage transition of the voltage on the word line Wa(1) generallycorresponds with the voltage transition of the voltage on the topelectrodes TE of the odd resistive change elements OO1 a, Ox1 a becausethe voltage on the word line Wa(1) generally corresponds with thevoltage on the top electrodes TE of the odd resistive change elementsOO1 a, Ox1 a. The voltage transitions of the voltages on the pluralityof odd bit lines Boa(0)-Boa(x) generally corresponds with the voltagetransitions of the voltages on the bottom electrodes BE of the oddresistive change elements OO1 a, Ox1 a because the voltages on theplurality of odd bit lines Boa(0)-Boa(x) generally corresponds with thevoltages on the bottom electrodes BE of the odd resistive changeelements OO1 a, Ox1 a. The magnitude of the voltage transition to placethe top electrodes TE of the odd resistive change elements OO1 a, Ox1 aat the system voltage VDD for generating voltages indicative ofresistive states of the odd resistive change elements OO1 a, Ox1 a isreduced because the voltage applied to the top electrodes TE of the oddresistive change elements OO1 a, Ox1 a is not required to transition bythe magnitude of the system voltage VDD. A voltage transition of thesystem voltage VDD minus the inhibit voltage VINH is required to placethe top electrodes at the system voltage VDD. For example, when theinhibit voltage VINH is VDD/2 (half of the system voltage VDD) a voltagetransition of VDD−VDD/2=VDD/2 is required to place the top electrodes atthe system voltage VDD. Further, the number of voltage transitions forgenerating voltages indicative of resistive states of the odd resistivechange elements OO1 a, Ox1 a is reduced because only voltages on theword line Wa(1), the plurality of global bit lines GB6(0)-GB6(x), andthe plurality of odd bit lines Boa(0)-Boa(x) are adjusted for generatingvoltages indicative of resistive states of the odd resistive changeelements OO1 a, Ox1 a. It is noted that applying the inhibit voltageVINH to a top electrode, a bottom electrode, or both a top electrode anda bottom electrode of a resistive change element limits a voltageapplied across a resistive change element to a voltage less than avoltage limit for disturbing a resistive state of a resistive changeelement while generating voltages indicative of resistive states of theodd resistive change elements O01 a, Ox1 a.

The voltage on the word line Wa(1) is driven from the inhibit voltageVINH to the system voltage VDD by changing the voltage supplied by theword line driver circuit 111 da from the inhibit voltage VINH to thesystem voltage VDD. The word line driver circuit 111 da changes fromsupplying the inhibit voltage VINH to the system voltage VDD based on asignal ITE1 a supplied by control logic, such as a processor, acontroller, and a microcontroller. The plurality of write buffercircuits 1500-150 x do not supply voltages based on the write setsignals WR00-WR0 x and the write reset signals WR10-WR1 x supplied bycontrol logic, such as a processor, a controller, and a microcontroller.The amount of current for a READ operation is sunk from each bus line ofthe plurality of bus lines BL60-BL6 x by the current source inelectrical communication with that bus line. The amount of current for aREAD operation is based on the amount of current that would flow througha resistor having an intermediate resistance and having the systemvoltage VDD applied to one terminal of the resistor and the inhibitvoltage VINH applied to the other terminal of the resistor. The amountof current that would flow through a resistor having an intermediateresistance and having the system voltage VDD applied to one terminal ofthe resistor and the inhibit voltage VINH applied to the other terminalof the resistor can be approximated by the following equation,I=(VDD−VINH)/Intermediate Resistance. For example, when the intermediateresistance=5.5MΩ, the system voltage VDD=2V, and the inhibit voltageVINH=1V, each current source of the plurality of current sources1600-160 x is configured to sink an amount of current that can beapproximated as I=(2V−1V)/5.5MΩ=0.18 μA. It is noted that, ignoringleakage currents, the amount of current for the READ operation flowsthrough each odd resistive change element O001 a,Ox1 a in electricalcommunication with word line Wa(1), each odd bit line of the pluralityof odd bit lines Boa(0)-Boa(x), each global bit line of the plurality ofglobal bit lines GB6(0)-GB6(x), and each bus line of the plurality ofbus lines BL60-BL6 x to each current source of the plurality of currentsources 1600-160 x.

The intermediate resistance sets a boundary for resistance values thatcorrespond with a low resistive state during READ operations andresistance values that correspond with a high resistive state duringREAD operations. The intermediate resistance is a design variable thatcan be selected by a circuit designer and the circuit designer typicallyselects an intermediate resistance greater than a model resistance for alow resistive state of a resistive change element and less than a modelresistance for a high resistive state of a resistive change element. Forexample, when a model resistance for a low resistive state of aresistive change element is 1MΩ and a model resistance for a highresistive state of a resistive change elements is 10MΩ, a circuitdesigner can select an intermediate resistance of 5.5MΩ so thatresistive change elements having a resistance less than approximately5.5MΩ are determined to have a low resistive state during READoperations and resistive change elements having a resistance greaterthan approximately 5.5MΩ are determined to have a high resistive stateduring READ operations. It is noted that the intermediate resistance isnot limited to a resistance at the exact midpoint between a modelresistance for a low resistive state of a resistive change element and amodel resistance for a high resistive state of a resistive changeelement, but rather the intermediate resistance can be closer the modelresistance for the low resistive state or the model resistance for thehigh resistive state.

FIG. 5G-1 shows a current IO01 a flowing through the resistive changeelement OO1 a from the top electrode TE to the bottom electrode BEbecause the top electrode TE is at the system voltage VDD and the bottomelectrode BE is at a voltage indicative of a resistive state of theresistive change element OO1 a. FIG. 5G-1 also shows a current IOx1 aflowing through the resistive change element Ox1 a from the topelectrode TE to the bottom electrode BE because the top electrode TE isat the system voltage VDD and the bottom electrode BE is at a voltageindicative of a resistive state of the resistive change element Ox1 a.While, ignoring leakage currents, the amount of the current flowingthrough the resistive change element OO1 a, the odd bit line Boa(0), theglobal bit line GB6(0), and the bus line BL60 are the same amount ofcurrent (the amount of current for the READ operation) and the amount ofthe current flowing through the resistive change element Ox1 a, the oddbit line Boa(x), the global bit line GB6(x), and the bus line BL6 x arethe same amount of current (the amount of current for the READoperation). Additionally, ignoring leakage currents, routing parasitics,and an on resistance of an odd selection device of the plurality of oddselection devices NoaO-Noax, the voltage on an odd bit line in theplurality of odd bit lines Boa(0)-Boa(x), the voltage on a global bitline in the plurality of global bit lines GB6(0)-GB6(x), and the voltageon a bus line in the plurality of bus lines BL60-BL6 x having the samecolumn number are generally the same voltage and the voltage on an oddbit line in the plurality of odd bit lines Boa(0)-Boa(x), the voltage ona global bit line in the plurality of global bit lines GB6(0)-GB6(x),and the voltage on a bus line in the plurality of bus lines BL60-BL6 xhaving the same column number are indicative of a resistive state of anodd resistive change element in the odd resistive change elements OO1 a,Ox1 a having the same column number. It is noted that the voltageindicative of a resistive state of the resistive change element OO1 a isdiscussed below with respect to the voltage VGB6(0) on the global bitline GB6(0) and the voltage indicative of a resistive state of theresistive change element Ox1 a is discussed below with respect to thevoltage VGB6(x) on the global bit line GB6(x).

The voltage VGB6(0) on the global bit line GB6(0), ignoring leakagecurrents, routing parasitics, and on resistance of the odd selectiondevice NoaO, can be approximated by subtracting the voltage drop acrossthe resistive change element OO1 a from the voltage VWa(1) on the wordline Wa(1). The voltage drop across the resistive change element OO1 acan be approximated using Ohm's Law. Thus, the voltage VGB6(0) on theglobal bit line GB6(0) can be approximated by the following equationVGB6(0)=VWa(1)−(IO01 a×RO01 a), where VWa(1) is the voltage on the wordline Wa(1), the current IO01 a is the current flowing through resistivechange element OO1 a, and RO01 a is the resistance of the resistivechange element OO1 a. As shown by this equation, the voltage VGB6(0) onthe global bit line GB6(0) changes when the resistance of the resistivechange element OO1 a changes because the voltage VWa(1) on the word lineWa(1) and the current IO01 a flowing through the resistive changeelement OO1 a are generally the same for READ operations. For example,when VWa(1)=2 volts, IO01 a=1/5.5 microamps, and RO01 a=5.5MΩ, thevoltage VGB6(0)=2V−(1/5.5 μA×5.5MΩ)=1V. For example, when VWa(1)=2volts, IO01 a=1/5.5 microamps, and RO01 a=1MΩ, the voltageVGB6(0)=2V−(1/5.5 μA×1MΩ)=1.82V. For example, when VWa(1)=2 volts, IO01a=1/5.5 microamps, and RO01 a=10MΩ, the voltage VGB3(0)=2V−(1/5.5μA×10MΩ)=0.182V.

The voltage VGB6(x) on the global bit line GB6(x), ignoring leakagecurrents, routing parasitics, and on resistance of the odd selectiondevice Noax, can be approximated by subtracting the voltage drop acrossthe resistive change element Ox1 a from the voltage VWa(1) on the wordline Wa(1). The voltage drop across the resistive change element Ox1 acan be approximated using Ohm's Law. Thus, the voltage VGB6(x) on theglobal bit line GB6(x) can be approximated by the following equationVGB6(x)=VWa(1)−(IOx1 a×ROx1 a), where VWa(1) is the voltage on the wordline Wa(1), the current IOx1 a is the current flowing through resistivechange element Ox1 a, and ROx1 a is the resistance of the resistivechange element Ox1 a. As shown by this equation, the voltage VGB6(x) onthe global bit line GB6(x) changes when the resistance of the resistivechange element Ox1 a changes because the voltage VWa(1) on the word lineWa(1) and the current IOx1 a flowing through the resistive changeelement Ox1 a are generally the same for READ operations. For example,when VWa(1)=2 volts, IOx1 a=1/5.5 microamps, and ROx1 a=5.5MΩ, thevoltage VGB6(x)=2V−(1/5.5 μA×5.5MΩ)=1V. For example, when VWa(1)=2volts, IOx1 a=1/5.5 microamps, and ROx1 a=1MΩ, the voltageVGB6(x)=2V−(1/5.5 μA×1MΩ)=1.82V. For example, when VWa(1)=2 volts, IOx1a=1/5.5 microamps, and ROx1 a=10MΩ, the voltage VGB6(x)=2V−(1/5.5μA×10MΩ)=0.182V.

FIG. 5G-1 also shows leakage currents flowing through the resistivechange elements O00 a, O0 ya in electrical communication with the oddbit line Boa(0), leakage currents flowing through the resistive changeelements Ox0 a, Oxya in electrical communication with the odd bit lineBoa(x), and leakage currents flowing through the resistive changeelements E01 a, Ex1 a in electrical communication with the word lineWa(1). The leakage currents are shown using dashed lines in FIG. 5G-1.Leakage currents flow through the resistive change elements O00 a, O0 yabecause the bottom electrodes of the resistive change elements O00 a, O0ya are at a voltage indicative of a resistive state of the resistivechange element O01 a and the top electrodes of the resistive changeelements O00 a, O0 ya are the inhibit voltage VINH. Leakage currentsflow through the resistive change elements Ox0 a, Oxya because thebottom electrodes of the resistive change elements Ox0 a, Oxya are at avoltage indicative of a resistive state of the resistive change elementOx1 a and the top electrodes of the resistive change elements Ox0 a,Oxya are the inhibit voltage VINH. Leakage currents flow throughresistive change elements E01 a, Ex1 a because the bottom electrodes ofthe resistive change elements E01 a, Ex1 a are at the inhibit voltageVINH and the top electrodes of the resistive change elements E01 a, Ex1a are at the system voltage VDD. It is noted that leakage currents mayflow through resistive change elements other than the resistive changeelements in electrical communication with the odd bit line Boa(0), theresistive change elements in electrical communication with the odd bitline Boa(x), and the resistive change elements in electricalcommunication with the word line Wa(1) because voltages on other linesmay be impacted by generating voltages indicative of resistive states ofthe odd resistive change elements O01 a, Ox1 a. It is also noted thatleakage currents generally do not flow through the plurality ofresistive change elements E00 z-Oxyz in Section Z because the bottomelectrodes of the plurality of resistive change elements E00 z-Oxyz areat the inhibit voltage VINH and the top electrodes of the plurality ofresistive change elements E00 z-Oxyz are at the inhibit voltage VINH. Itis additionally noted that leakage currents do not prevent the READoperation of the odd resistive change elements O01 a, Ox1 a when theleakage currents are much less than the amounts of the current IO01 aand the current IOx1 a. It is further noted that the voltage differencesacross the resistive change elements that cause the leakage currents donot disturb the resistive states of the resistive change elementsbecause the voltage differences are less than a voltage limit fordisturbing a resistive state of a resistive change element.

FIG. 5G-1 shows leakage currents flowing through the resistive changeelements O00 a, O0 ya from the odd bit line Boa(0) because the resistivechange element O01 a has a low resistive state and a voltage indicativeof a low resistive state of resistive change element O01 a is greaterthan the inhibit voltage VINH. FIG. 5G-1 shows leakage currents flowingthrough the resistive change elements Ox0 a, Oxya into the odd bit lineBoa(x) because the resistive change element Ox1 a has a high resistivestate and a voltage indicative of a high resistive state of resistivechange element Ox1 a is greater than the inhibit voltage VINH. It isnoted that when the voltage VBoa(0) on the odd bit line Boa(0) is lessthan the inhibit voltage VINH and the word lines Wa(0), Wa(y) inelectrical communication with the other resistive change elements O00 a,O0 ya on the odd bit line Boa(0) are driven to the inhibit voltage VINH,leakage currents flow into the odd bit line Boa(0) through the otherresistive change elements O00 a, O0 ya and pull up the voltage VBoa(0)on the odd bit line Boa(0). It is also noted that when the voltageVBoa(0) on the odd bit line Boa(0) is greater than the inhibit voltageVINH and the word lines Wa(0), Wa(y) in electrical communication withthe other resistive change elements O00 a, O0 ya on the odd bit lineBoa(0) are driven to the inhibit voltage VINH, leakage currents flowfrom the odd bit line Boa(0) through the other resistive change elementsO00 a, O0 ya and pull down the voltage VBoa(0) on the bit line Boa(0).It is noted that when the voltage VBoa(x) on the odd bit line Boa(x) isless than the inhibit voltage VINH and the word lines Wa(0), Wa(y) inelectrical communication with the other resistive change elements Ox0 a,Oxya on the odd bit line Boa(x) are driven to the inhibit voltage VINH,leakage currents flow into the odd bit line Boa(x) through the otherresistive change elements Ox0 a, Oxya and pull up the voltage VBoa(x) onthe odd bit line Boa(x). It is also noted that when the voltage VBoa(x)on the odd bit line Boa(x) is greater than the inhibit voltage VINH andthe word lines Wa(0), Wa(y) in electrical communication with the otherresistive change elements Ox0 a, Oxya on the odd bit line Boa(x) aredriven to the inhibit voltage VINH, leakage currents flow from the oddbit line Boa(x) through the other resistive change elements Ox0 a, Oxyaand pull down the voltage VBoa(x) on the bit line Boa(x). It is furthernoted that when voltages on the plurality of odd bit lines Boa(0)-Boa(x)are pulled up by leakage currents flowing into the plurality of odd bitlines Boa(0)-Boa(x), when voltages on the plurality of odd bit linesBoa(0)-Boa(a) are pulled down by leakage currents flowing from theplurality of bit lines Boa(0)-Boa(x), and when a voltage on at least oneodd bit line of the plurality of odd bit lines Boa(0)-Boa(x) is pulledup by leakage currents flowing into the at least one odd bit line and avoltage on at least one other odd bit line of the plurality of odd bitlines Boa(0)-Boa(x) is pulled down by leakage currents flowing from theat least one other odd bit line, the number of the word lines Wa(0),Wa(y) should be small enough to allow a margin to determine resistivestates of the odd resistive change elements O01 a, Ox1 a.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A proceeds, as similarlydiscussed above in step 412 of the flow chart 400, by determining theresistive states of the odd resistive change elements O01 a, Ox1 a basedon the voltages VGB6(0)-VGB6(x) on the plurality of global bit linesGB6(0)-GB6(x). As discussed above, a voltage indicative of a resistivestate of an odd resistive change element in the odd resistive changeelements O01 a, Ox1 a is generated on a global bit line in the pluralityof global bit lines GB6(0)-GB6(x) having the same column number as theodd resistive change element. The resistive state of the resistivechange element O01 a is determined by comparing the voltage VGB6(0) onwith global bit line GB6(0) with the inhibit voltage VINH on thereference line RL6 and the resistive state of the resistive changeelement Ox1 a is determined by comparing the voltage VGB6(x) on withglobal bit line GB6(x) with the inhibit voltage VINH on the referenceline RL6. For READ operations the inhibit voltage VINH is indicative ofthe intermediate resistance because the inhibit voltage VINH is equal tothe system voltage VDD minus a voltage calculated by multiplying theamount of current for a READ operation and the intermediate resistanceof 5.5MΩ. For example, when the system voltage VDD=2V, the inhibitvoltage VINH=1V, the amount of current for READ operations=1/5.5 μA, andthe intermediate resistance=5.5MΩ, VINH=2V−(1/5.5 μA×5.5MΩ)=1V.

When the voltage VGB6(0) on the global bit line GB6(0) is greater thanthe inhibit voltage (i.e. the voltage VGB6(0) on the global bit lineGB6(0)>VINH) the resistance of the resistive change element OO1 a isless than the intermediate resistance (i.e. RO01 a<intermediateresistance, where RO01 a is the resistance of the resistive changeelement OO1 a) and the resistive state of the resistive change elementOO1 a is determined to be a low resistive state. When the voltageVGB6(0) on the global bit line GB6(0) is less than the inhibit voltageVINH (i.e. the voltage VGB6(0) on the global bit line GB6(0)<VINH) theresistance of the resistive change element OO1 a is greater than theintermediate resistance (i.e. RO01 a>intermediate resistance, where RO01a is the resistance of the resistive change element OO1 a) and theresistive state of resistive change element OO1 a is determined to be ahigh resistive state.

When the voltage VGB6(x) on the global bit line GB6(x) is greater thanthe inhibit voltage (i.e. the voltage VGB6(x) on the global bit lineGB6(x)>VINH) the resistance of the resistive change element Ox1 a isless than the intermediate resistance (i.e. ROx1 a<intermediateresistance, where ROx1 a is the resistance of the resistive changeelement Ox1 a) and the resistive state of the resistive change elementOx1 a is determined to be a low resistive state. When the voltageVGB6(x) on the global bit line GB6(x) is less than the inhibit voltageVINH (i.e. the voltage VGB6(x) on the global bit line GB6(x)<VINH) theresistance of the resistive change element Ox1 a is greater than theintermediate resistance (i.e. ROx1 a>intermediate resistance, where ROx1a is the resistance of the resistive change element Ox1 a) and theresistive state of resistive change element Ox1 a is determined to be ahigh resistive state.

As shown in FIG. 5G-4, the first input device 5100 receives the voltageVGB6(0) on the global bit line GB6(0), the inhibit voltage VINH from apower supply, a voltage source, a driver circuit, or other device thatsupplies the inhibit voltage VINH, the initialization signal INIT, andthe complementary initialization signal INITB. The first input device510 x receives the voltage VGB6(x) on the global bit line GB6(x), theinhibit voltage VINH from a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH, theinitialization signal INIT, and the complementary initialization signalINITB. The second input device 5200 receives the inhibit voltage VINH onthe reference line RL6, the inhibit voltage VINH from a power supply, avoltage source, a driver circuit, or other device that supplies theinhibit voltage VINH, the initialization signal INIT, and thecomplementary initialization signal INITB. When the initializationsignal INIT has a low level and the complementary initialization signalINITB has a high level, the first input device 5100 supplies the voltageVGB6(0) on the global bit line GB6(0) to the sense amplifier 5500, thefirst input device 510 x supplies the voltage VGB6(x) on the global bitline GB6(x) to the sense amplifier 550 x, and the second input device5200 supplies the inhibit voltage VINH on the reference line RL6 to thesense amplifier 5500 and the sense amplifier 550 x. When theinitialization signal INIT has a high level and the complementaryinitialization signal INITB has a low level, the first input device 5100supplies the inhibit voltage VINH from a power supply, a voltage source,a driver circuit, or other device that supplies the inhibit voltage VINHto the sense amplifier 5500, the first input device 510 x supplies theinhibit voltage VINH from a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH to thesense amplifier 550 x, and the second input device 5200 supplies theinhibit voltage VINH from a power supply, a voltage source, a drivercircuit, or other device that supplies the inhibit voltage VINH to thesense amplifier 5500 and the sense amplifier 550 x.

When the initialization signal INIT has a low level and thecomplementary initialization signal INITB has a high level the senseamplifier 5500 receives the voltage VGB6(0) on the global bit lineGB6(0) and the inhibit voltage VINH on the reference line RL6. The senseamplifier 5500 determines the resistive state of the resistive changeelement O01 a by comparing the inhibit voltage VINH on the referenceline RL6 with the voltage VGB6(0) on the global bit line GB6(0). Thesense amplifier 5500 outputs signals indicative of the resistive stateof the resistive change element O01 a on two outputs. When the voltageVGB6(0) on the global bit line GB6(0) is greater than the inhibitvoltage VINH, the sense amplifier 5500 outputs signals indicating theresistive change element O01 a has a low resistive state. When thevoltage VGB6(0) on the global bit line GB6(0) is less than the inhibitvoltage VINH, the sense amplifier 5500 outputs signals indicating theresistive change element O01 a has a high resistive state. When thesense amplifier 5500 is a second sense amplifier, the sense amplifier6O00 operates in the same manner as the second sense amplifier 600discussed above. When the sense amplifier 5500 is a third senseamplifier, the sense amplifier 5500 operates in the same manner as thethird sense amplifier 700 discussed above. It is noted that providingthe inhibit voltage VINH on the reference line RL6 to the senseamplifier 5500 can increase the accuracy of determining the resistivestate of the resistive change element O01 a because the inhibit voltageVINH on the reference line RL6 and the voltage VGB6(0) on the global bitline GB6(0) are subject to similar conditions.

When the initialization signal INIT has a low level and thecomplementary initialization signal INITB has a high level the senseamplifier 550 x receives the voltage VGB6(x) on the global bit lineGB6(x) and the inhibit voltage VINH on the reference line RL6. The senseamplifier 550 x determines the resistive state of the resistive changeelement Ox1 a by comparing the inhibit voltage VINH on the referenceline RL6 with the voltage VGB6(x) on the global bit line GB6(x). Thesense amplifier 550 x outputs signals indicative of the resistive stateof the resistive change element Ox1 a on two outputs. When the voltageVGB6(x) on the global bit line GB6(x) is greater than the inhibitvoltage VINH, the sense amplifier 550 x outputs signals indicating theresistive change element Ox1 a has a low resistive state. When thevoltage VGB6(x) on the global bit line GB6(x) is less than the inhibitvoltage VINH, the sense amplifier 550 x outputs signals indicating theresistive change element Ox1 a has a high resistive state. When thesense amplifier 550 x is a second sense amplifier, the sense amplifier550 x operates in the same manner as the second sense amplifier 600discussed above. When the sense amplifier 550 x is a third senseamplifier, the sense amplifier 550 x operates in the same manner as thethird sense amplifier 700 discussed above. It is noted that providingthe inhibit voltage VINH on the reference line RL6 to the senseamplifier 550 x can increase the accuracy of determining the resistivestate of the resistive change element Ox1 a because the inhibit voltageVINH on the reference line RL6 and the voltage VGB6(x) on the global bitline GB6(x) are subject to similar conditions.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A proceeds, as similarlydiscussed above in step 414 of the flow chart 400, by restoring neutralvoltage conditions for resistive change elements impacted by generatingvoltages indicative of resistive states of the odd resistive changeelements O01 a, Ox1 a. Neutral voltage conditions are restored forresistive change elements impacted by generating voltages indicative ofresistive states of the odd resistive change elements O01 a, Ox1 a byfloating the plurality of odd bit lines Boa(0)-Boa(x) and applying theinhibit voltage VINH to the word line Wa(1). The plurality of even bitlines Bea(0)-Bea(x) are already floating because the plurality of evenselection devices Nea0-Neax are turned off. The inhibit voltage VINH isalready applied to the word lines Wa(0), Wa(y) because the word linedriver circuits 110 da, 11 yda are already supplying the inhibit voltageVINH. The plurality of odd bit lines Boa(0)-Boa(x) are floated bydisconnecting the plurality of odd bit lines Boa(0)-Boa(x) from theplurality of global bit lines GB6(0)-GB6(x) by turning off the pluralityof odd selection devices Noa0-Noax. The plurality of odd selectiondevices Noa0-Noax are turned off by control logic, such as a processor,a controller, and a microcontroller, supplying a signal SSELo having alow level. The inhibit voltage VINH is applied to the word line Wa(1) bythe word line driver circuit 111 da driving the voltage on the word lineWa(1) to the inhibit voltage VINH. The word line driver circuit 111 dasupplies the inhibit voltage VINH based on the signal ITE1 a supplied bycontrol logic, such as a processor, a controller, and a microcontroller.Thus, the inhibit voltage VINH is applied to the plurality of word linesWa(0)-Wa(y) with the plurality of even bit lines Bea(0)-Bea(x) and theplurality of odd bit lines Boa(0)-Boa(x) floating so that voltagesapproximately equal to the inhibit voltage VINH are applied to the topelectrodes and the bottom electrodes of the resistive change elements inthe plurality of resistive change elements E00 a-Oxya.

The READ operation of odd resistive change elements in electricalcommunication with word line Wa(1) in Section A continues, as similarlydiscussed above in step 416 of the flow chart 400, by biasing global bitlines impacted by generating voltages indicative of resistive states ofthe odd resistive change elements O01 a, Ox1 a. Global bit linesimpacted by generating voltages indicative of resistive states of theodd resistive change elements O01 a, Ox1 a are biased to the inhibitvoltage VINH by floating the plurality of global bit lines GB6(0)-GB6(x)and applying the inhibit voltage VINH to the plurality of global bitlines GB6(0)-GB6(x). The plurality of global bit lines GB6(0)-GB6(x) arefloated by disconnecting the plurality of global bit lines GB6(0)-GB6(x)from the plurality of odd bit lines Boa(0)-Boa(x) and disconnecting theplurality of global bit lines GB6(0)-GB6(x) from the plurality of buslines BL60-BL6 x. The plurality of global bit lines GB6(0)-GB6(x) arealready disconnected from the plurality of even bit lines Bea(0)-Bea(x)because the plurality of even selection devices Nea0-Neax are turned offThe plurality of global bit lines GB6(0)-GB6(x) may be disconnected fromthe plurality of odd bit lines Boa(0)-Boa(x) as part of restoringneutral voltage conditions for resistive change elements impacted bygenerating voltages indicative of resistive states of the odd resistivechange elements O01 a, Ox1 a as discussed above. The plurality of globalbit lines GB6(0)-GB6(x) are disconnected from the plurality of bus linesBL60-BL6 x by turning off the plurality of PMOS transistors 590 g-59 xg.The plurality of PMOS transistors 590 g-59 xg are turned off by controllogic, such as a processor, a controller, and a microcontroller,supplying a signal CD0 having a high level. The inhibit voltage VINH isapplied to the plurality of global bit lines GB6(0)-GB6(x) byelectrically connecting the plurality of global bit lines GB6(0)-GB6(x)to a power supply, a voltage source, a driver circuit, or other devicethat supplies the inhibit voltage VINH by turning on the plurality ofNMOS transistors 130 k-13 xk. The plurality of NMOS transistors 130 k-13xk are turned on by control logic, such as a processor, a controller,and a microcontroller, supplying a signal KEEPe having a high level anda signal KEEPo having a high level. It is noted that control logic, suchas a processor, a controller, and a microcontroller, supplying a signalCDO having a high level also turns off the PMOS transistor 590 r in theglobal bit line connection circuit 590.

SET VERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of resistive change elementarray 101 in the exemplary DDR compatible implementation of the secondexemplary architecture and SET VERIFY operations of even resistivechange elements in electrical communication with a word line in asection of resistive change element array 101 in the exemplary DDRcompatible implementation of the second exemplary architecture can beperformed in a similar manner to the READ operations of odd resistivechange elements in electrical communication with word line Wa(1)discussed above, but with each current source of the plurality ofcurrent sources 1600-160 x set to sink an amount of current for a SETVERIFY operation. The amount of current for a SET VERIFY operation isbased on the amount of current that would flow through a resistor havinga low resistance and having the system voltage VDD applied to oneterminal of the resistor and the inhibit voltage VINH applied to theother terminal of the resistor. The amount of current that would flowthrough a resistor having a low resistance and having the system voltageVDD applied to one terminal of the resistor and the inhibit voltage VINHapplied to the other terminal of the resistor can be approximated by thefollowing equation, I=(VDD−VINH)/Low Resistance. For example, when thelow resistance is 2MΩ, the system voltage VDD is 2V, and the inhibitvoltage VINH is 1V, each current source of the plurality of currentsources 1600-160 x is configured to sink an amount of current for a SETVERIFY operation that can be approximated as I=(2V−1V)/2MΩ=0.5 μA.

The low resistance sets an upper boundary for resistance values thatcorrespond with a low resistive state during SET VERIFY operations. Thelow resistance is a design variable that can be selected by a circuitdesigner and the circuit designer typically selects a low resistancegreater than a model resistance for a low resistive state of a resistivechange element so that resistive change elements can have resistancesgreater than the model resistance for the low resistive state and bedetermined to have a low resistive state during SET VERIFY operations.For example, when a model resistance for a low resistive state of aresistive change element is 1MΩ, a circuit designer can select a lowresistance of 2MΩ so that resistive change elements having a resistanceless than approximately 2MΩ are determined to have a low resistive stateduring SET VERIFY operations. It is noted that the circuit designertypically selects a low resistance greater than a model resistance for alow resistive state of a resistive change element and less than anintermediate resistance for READ operations.

RESET VERIFY operations of odd resistive change elements in electricalcommunication with a word line in a section of resistive change elementarray 101 in the exemplary DDR compatible implementation of the secondexemplary architecture and RESET VERIFY operations of even resistivechange elements in electrical communication with a word line in asection of resistive change element array 101 in the exemplary DDRcompatible implementation of the second exemplary architecture can beperformed in a similar manner to the READ operations of odd resistivechange elements in electrical communication with word line Wa(1)discussed above, but with each current source of the plurality ofcurrent sources 1600-160 x set to sink an amount of current for a RESETVERIFY operation. The amount of current for a RESET VERIFY operation isbased on the amount of current that would flow through a resistor havinga high resistance and having the system voltage VDD applied to oneterminal of the resistor and the inhibit voltage VINH applied to theother terminal of the resistor. The amount of current that would flowthrough a resistor having a high resistance and having the systemvoltage VDD applied to one terminal of the resistor and the inhibitvoltage VINH applied to the other terminal of the resistor can beapproximated by the following equation, I=(VDD−VINH)/High Resistance.For example, when the high resistance is 9MΩ, the system voltage VDD is2V, and the inhibit voltage VINH is 1V, each current source of theplurality of current sources 1600-160 x is configured to sink an amountof current for a RESET VERIFY operation that can be approximated asI=(2V−1V)/9MΩ=0.11 μA.

The high resistance sets an upper boundary for resistance values thatcorrespond with a high resistive state during RESET VERIFY operations.The high resistance is a design variable that can be selected by acircuit designer and the circuit designer typically selects a highresistance less than a model resistance for a high resistive state of aresistive change element so that resistive change elements can haveresistances less than the model resistance for the high resistive stateand be determined to have a high resistive state during RESET VERIFYoperations. For example, when a model resistance for a high resistivestate of a resistive change element is 10MΩ, a circuit designer canselect a high resistance of 9MΩ so that resistive change elements havinga resistance greater than approximately 9MΩ are determined to have ahigh resistive state during RESET VERIFY operations. It is noted thatthe circuit designer typically selects a high resistance less than amodel resistance for a high resistive state of a resistive changeelement and greater than an intermediate resistance for READ operations.

Although the present disclosure has been described in relation toparticular embodiments thereof, many other variations and modificationand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present disclosure not be limited by thespecific disclosure herein.

What is claimed is:
 1. A sense amplifier comprising: a first load devicecomprising a first plurality of field effect transistors; a second loaddevice comprising a second plurality of field effect transistors,wherein said second load device is in electrical communication with saidfirst load device; a current source in electrical communication withsaid first load device and said second load device; a latch device; apower control device in electrical communication with said first loaddevice, said second load device, and said latch device; and said senseamplifier being configurable in an initializing configuration and acomparing configuration, wherein said first load device is configurableto generate a first bias voltage in said initializing configuration andto set an operating point of a field effect transistor of said firstplurality of field effect transistors based on said first bias voltagein said comparing configuration, and wherein said second load device isconfigurable to generate a second bias voltage in said initializingconfiguration and to set an operating point of a field effect transistorof said second plurality of field effect transistors based on saidsecond bias voltage in said comparing configuration.
 2. The senseamplifier of claim 1, wherein said first plurality of field effecttransistors comprises a first plurality of capacitor connected PMOStransistors and wherein said second plurality of field effecttransistors comprises a second plurality of capacitor connected PMOStransistors.
 3. The sense amplifier of claim 2, wherein said firstplurality of capacitor connected PMOS transistors are chargeable to saidfirst bias voltage in said initializing configuration and said secondplurality of capacitor connected PMOS transistors are chargeable to saidsecond bias voltage in said initializing configuration.
 4. The senseamplifier of claim 3, wherein a capacitor connected PMOS transistor ofsaid first plurality of capacitor connected PMOS transistors is inelectrical communication with said second load device and wherein acapacitor connected PMOS transistor of said second plurality ofcapacitor connected PMOS transistors is in electrical communication withsaid first load device.
 5. The sense amplifier of claim 1, wherein saidfirst load device is configured to receive a first signal and a secondsignal, wherein said second load device is configured to receive saidfirst signal and said second signal, and wherein said sense amplifier isconfigurable in said initializing configuration and said comparingconfiguration based on said first signal and said second signal.
 6. Thesense amplifier of claim 5, further comprising: a first input device inelectrical communication with said first load device, wherein said firstinput device is configured to receive a first voltage, a second voltage,said first signal, and said second signal, wherein said first inputdevice is configured to provide one of said first voltage and saidsecond voltage to said first load device based on said first signal andsaid second signal; and a second input device in electricalcommunication with said second load device, wherein said second inputdevice is configured to receive a third input voltage, said firstsignal, and said second signal, wherein said second input device isconfigured to provide said third voltage to said second load devicebased on said first signal and said second signal.
 7. The senseamplifier of claim 5, wherein said first load device is configured toreceive a first voltage and wherein said second load device isconfigured to receive a second voltage.
 8. The sense amplifier of claim1, further comprising: a first coupling canceller in electricalcommunication with said first load device and said second load device;and a second coupling canceller in electrical communication with saidfirst load device and said second load device.
 9. The sense amplifier ofclaim 8, wherein said first coupling canceller comprises a capacitorconnected NMOS transistor in electrical communication with said firstload device and said second load device and wherein said second couplingcanceller comprises a capacitor connected NMOS transistor in electricalcommunication with said first load device and said second load device.10. The sense amplifier of claim 1, further comprising: a first voltageswing limiter in electrical communication with said first load deviceand said second load device; a second voltage swing limiter inelectrical communication with said first load device and said secondload device; and said first voltage swing limiter and said secondvoltage swing limiter are operable together to limit a voltagedifference between a voltage generated by said first load device and avoltage generated by said second load device.
 11. The sense amplifier ofclaim 10, wherein said first voltage swing limiter comprises: a NMOStransistor having a drain terminal, a gate terminal, and a sourceterminal; a PMOS transistor having a drain terminal, a gate terminal,and a source terminal; and wherein said gate terminal of said NMOStransistor is in electrical communication with said first load deviceand said gate terminal of said PMOS transistor, said source terminal ofsaid NMOS transistor is in electrical communication with said secondload device and said source terminal of said PMOS transistor, andwherein said gate terminal of said PMOS transistor is in electricalcommunication with said first load device and said gate terminal of saidNMOS transistor, and said source terminal of said PMOS transistor is inelectrical communication with said second load device and said sourceterminal of said NMOS transistor.
 12. The sense amplifier of claim 11,wherein said second voltage swing limiter comprises: a NMOS transistorhaving a drain terminal, a gate terminal, and a source terminal; a PMOStransistor having a drain terminal, a gate terminal, and a sourceterminal; and wherein said gate terminal of said NMOS transistor is inelectrical communication with said second load device and said gateterminal of said PMOS transistor, said source terminal of said NMOStransistor is in electrical communication with said first load deviceand said source terminal of said PMOS transistor, and wherein said gateterminal of said PMOS transistor is in electrical communication withsaid second load device and said gate terminal of said NMOS transistor,and said source terminal of said PMOS transistor is in electricalcommunication with said first load device and said source terminal ofsaid NMOS transistor.
 13. The sense amplifier of claim 1, wherein saidcurrent source is configured to sink current.
 14. A sense amplifiercomprising: a first load device comprising a first plurality of fieldeffect transistors; a second load device comprising a second pluralityof field effect transistors, wherein said second load device is inelectrical communication with said first load device; a current sourcein electrical communication with said first load device and said secondload device; a latch device; a power control device in electricalcommunication with said first load device, said second load device, andsaid latch device; and said sense amplifier being configurable in aninitializing configuration and a comparing configuration, wherein saidfirst load device is configurable to create a current path through saidfirst load device in said initializing configuration and to create acurrent path through said first load device in said comparingconfiguration, wherein a first field effect transistor of said firstplurality of field effect transistors is in said current path throughsaid first load device in said initializing configuration and is in saidcurrent path through said first load device in said comparingconfiguration, wherein said first field effect transistor of said firstplurality of field effect transistors is configured to function as adiode in said initializing configuration and is configured to functionas a resistor in said comparing configuration, wherein said second loaddevice is configurable to create a current path through said second loaddevice in said initializing configuration and to create a current paththrough said second load device in said comparing configuration, whereina first field effect transistor of said second plurality of field effecttransistors is in said current path through said second load device insaid initializing configuration and is in said current path through saidsecond load device in said comparing configuration, and wherein saidfirst field effect transistor of said second plurality of field effecttransistors is configured to function as a diode in said initializingconfiguration and is configured to function as a resistor in saidcomparing configuration.
 15. The sense amplifier of claim 14, whereinsaid first field effect transistor of said first plurality of fieldeffect transistors is a PMOS transistor and wherein said first fieldeffect transistor of said second plurality of field effect transistorsis a PMOS transistor.
 16. The sense amplifier of claim 14, wherein asecond field effect transistor of said first plurality of field effecttransistors is in said current path through said first load device insaid initializing configuration and is in said current path through saidfirst load device in said comparing configuration and wherein a secondfield effect transistor of said second plurality of field effecttransistors is in said current path through said second load device insaid initializing configuration and is in said current path through saidsecond load device in said comparing configuration.
 17. The senseamplifier of claim 16, wherein said second field effect transistor ofsaid first plurality of field effect transistors is a NMOS transistorand wherein said second field effect transistor of said second pluralityof field effect transistors is a NMOS transistor.
 18. The senseamplifier of claim 16, wherein said second field effect transistor ofsaid first plurality of field effect transistors is configured tofunction as a diode in said initializing configuration and wherein saidsecond field effect transistor of said second plurality of field effecttransistors is configured to function as a diode in said initializingconfiguration.
 19. The sense amplifier of claim 18, wherein said firstplurality of field effect transistors comprises a capacitor connectedNMOS transistor, wherein said capacitor connected NMOS transistor ofsaid first plurality of field effect transistors is in electricalcommunication with said second field effect transistor of said firstplurality of field effect transistors, wherein said second plurality offield effect transistors comprises a capacitor connected NMOStransistor, and wherein said capacitor connected NMOS transistor of saidsecond plurality of field effect transistors is in electricalcommunication with said second field effect transistor of said secondplurality of field effect transistors.
 20. The sense amplifier of claim14, wherein said first plurality of field effect transistors comprises afirst plurality of capacitor connected PMOS transistors and wherein saidsecond plurality of field effect transistors comprises a secondplurality of capacitor connected PMOS transistors.
 21. The senseamplifier of claim 20, wherein a capacitor connected PMOS transistor ofsaid first plurality of capacitor connected PMOS transistors is inelectrical communication with said second load device and wherein acapacitor connected PMOS transistor of said second plurality ofcapacitor connected PMOS transistors is in electrical communication withsaid first load device.
 22. The sense amplifier of claim 14, whereinsaid first load device is configured to receive a first signal and asecond signal, wherein said second load device is configured to receivesaid first signal and said second signal, and wherein said senseamplifier is configurable in said initializing configuration and saidcomparing configuration based on said first signal and said secondsignal.
 23. The sense amplifier of claim 22, further comprising: a firstinput device in electrical communication with said first load device,wherein said first input device is configured to receive a firstvoltage, a second voltage, said first signal, and said second signal,wherein said first input device is configured to provide one of saidfirst voltage and said second voltage to said first load device based onsaid first signal and said second signal; and a second input device inelectrical communication with said second load device, wherein saidsecond input device is configured to receive a third input voltage, saidfirst signal, and said second signal, wherein said second input deviceis configured to provide said third voltage to said second load devicebased on said first signal and said second signal.
 24. The senseamplifier of claim 22, wherein said first load device is configured toreceive a first voltage and wherein said second load device isconfigured to receive a second voltage.
 25. The sense amplifier of claim14, further comprising: a first coupling canceller in electricalcommunication with said first load device and said second load device;and a second coupling canceller in electrical communication with saidfirst load device and said second load device.
 26. The sense amplifierof claim 25, wherein said first coupling canceller comprises a capacitorconnected NMOS transistor in electrical communication with said firstload device and said second load device and wherein said second couplingcanceller comprises a capacitor connected NMOS transistor in electricalcommunication with said first load device and said second load device.27. The sense amplifier of claim 14, further comprising: a first voltageswing limiter in electrical communication with said first load deviceand said second load device; a second voltage swing limiter inelectrical communication with said first load device and said secondload device; and said first voltage swing limiter and said secondvoltage swing limiter are operable together to limit a voltagedifference between a voltage generated by said first load device and avoltage generated by said second load device.
 28. The sense amplifier ofclaim 27, wherein said first voltage swing limiter comprises: a NMOStransistor having a drain terminal, a gate terminal, and a sourceterminal; a PMOS transistor having a drain terminal, a gate terminal,and a source terminal; and wherein said gate terminal of said NMOStransistor is in electrical communication with said first load deviceand said gate terminal of said PMOS transistor, said source terminal ofsaid NMOS transistor is in electrical communication with said secondload device and said source terminal of said PMOS transistor, andwherein said gate terminal of said PMOS transistor is in electricalcommunication with said first load device and said gate terminal of saidNMOS transistor and said source terminal of said PMOS transistor is inelectrical communication with said second load device and said sourceterminal of said NMOS transistor.
 29. The sense amplifier of claim 28,wherein said second voltage swing limiter comprises: a NMOS transistorhaving a drain terminal, a gate terminal, and a source terminal; a PMOStransistor having a drain terminal, a gate terminal, and a sourceterminal; and wherein said gate terminal of said NMOS transistor is inelectrical communication with said second load device and said gateterminal of said PMOS transistor, said source terminal of said NMOStransistor is in electrical communication with said first load deviceand said source terminal of said PMOS transistor, and wherein said gateterminal of said PMOS transistor is in electrical communication withsaid second load device and said gate terminal of said NMOS transistor,and said source terminal of said PMOS transistor is in electricalcommunication with said first load device and said source terminal ofsaid NMOS transistor.
 30. The sense amplifier of claim 14, wherein saidcurrent source is configured to sink current.